4b5b 8b10b接线完成

src/test/scala/SimCDR.scala

@@ -27,6 +27,13 @@ class SimCDR extends Module with RequireAsyncReset{
   val dataCnt = RegInit(0.U(12.W))
   val payloadLen = RegInit(("hFFF".U)(12.W))
 
+  val b4b5Encoder = Module(new b4b5DualEncode)
+  val b4b5Decoder = Module(new b4b5DualDecode)
+
+  val b8b10Encoder = Module(new b8b10Encode)
+  val b8b10Decoder = Module(new b8b10Decode)
+
+
    
   when( cdrOut.io.axis.fire & dataCnt === 0.U ){
     payloadLen := Cat( io.data, 0.U(4.W) )
@@ -72,6 +79,28 @@ class SimCDR extends Module with RequireAsyncReset{
   io.isFailed  := cdrIn.io.axis.fire & (record.io.deq.bits =/= cdrIn.io.axis.bits.tdata)
   io.isSuccess := cdrIn.io.axis.fire & cdrIn.io.axis.bits.tlast
 
+
+
+
+  val isUsing8b10b = true.B
+
+
+  when( isUsing8b10b ){
+    b8b10Encoder.io <> cdrOut.io.encode
+    b8b10Decoder.io <> cdrIn.io.decode
+
+    b4b5Encoder.io.isEnable := false.B
+    b4b5Encoder.io.dataIn := 0.U
+    b4b5Decoder.io.dataIn := 0.U
+  } .otherwise{
+    b4b5Encoder.io <> cdrOut.io.encode
+    b4b5Decoder.io <> cdrIn.io.decode
+
+    b8b10Encoder.io.isEnable := false.B
+    b8b10Encoder.io.dataIn := 0.U
+    b8b10Decoder.io.dataIn := 0.U
+  }
+
 }