compare test pass

.metals/metals.lock.db

@@ -1,6 +1,6 @@
 #FileLock
-#Sun Jun 18 13:05:58 UTC 2023
+#Tue Jun 20 09:28:51 IRKT 2023
-server=localhost\:43909
 hostName=localhost
+id=188d66b3b3748481f5b9d61add429f6624c89a575b9
 method=file
-id=188ce9cbab0d7600f0e447af9df2123be91298d838e
+server=localhost\:58608

Makefile

@@ -0,0 +1,8 @@
+
+.PHONY: compile
+
+compile:
+	rm -rf ./generated/Main/
+	sbt "test:runMain test.testModule \
+	-e verilog"
+

build.sbt

@@ -4,7 +4,7 @@ ThisBuild / scalaVersion     := "2.13.8"
 ThisBuild / version          := "0.1.0"
 ThisBuild / organization     := "%ORGANIZATION%"
 
-val chiselVersion = "3.5.4"
+val chiselVersion = "3.5.6"
 
 lazy val root = (project in file("."))
   .settings(

generated/MIIM.anno.json

@@ -0,0 +1,18 @@
+[
+  {
+    "class":"firrtl.EmitAllModulesAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"generated/"
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~MIIM|MIIM>io_Busy",
+    "sources":[
+      "~MIIM|MIIM>io_RStat",
+      "~MIIM|MIIM>io_WCtrlData"
+    ]
+  }
+]

generated/MIIM.fir

@@ -0,0 +1,355 @@
+circuit MIIM :
+  module MIIM :
+    input clock : Clock
+    input reset : UInt<1>
+    output io : { flip mdi : UInt<1>, mdc : UInt<1>, mdo : UInt<1>, mdoEn : UInt<1>, flip Divider : UInt<8>, flip NoPre : UInt<1>, flip WCtrlData : UInt<1>, flip CtrlData : UInt<16>, flip Fiad : UInt<5>, flip Rgad : UInt<5>, flip RStat : UInt<1>, flip ScanStat : UInt<1>, Busy : UInt<1>, LinkFail : UInt<1>, Nvalid : UInt<1>, Prsd : UInt<16>, WCtrlDataStart : UInt<1>, RStatStart : UInt<1>, UpdateMIIRX_DATAReg : UInt<1>}
+
+    wire ByteSelect : UInt<1>[4] @[MII.scala 42:24]
+    reg Counter : UInt<8>, clock with :
+      reset => (reset, UInt<8>("h1")) @[MII.scala 46:25]
+    reg mdc : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[MII.scala 47:20]
+    node _mdcEn_T = eq(Counter, UInt<1>("h0")) @[MII.scala 48:27]
+    node _mdcEn_T_1 = not(mdc) @[MII.scala 48:38]
+    node mdcEn = and(_mdcEn_T, _mdcEn_T_1) @[MII.scala 48:36]
+    node _mdcEn_n_T = eq(Counter, UInt<1>("h0")) @[MII.scala 49:27]
+    node mdcEn_n = and(_mdcEn_n_T, mdc) @[MII.scala 49:36]
+    reg ShiftReg : UInt<8>, clock with :
+      reset => (reset, UInt<8>("h0")) @[MII.scala 51:25]
+    reg Prsd : UInt<16>, clock with :
+      reset => (reset, UInt<16>("h0")) @[MII.scala 52:25]
+    reg LinkFail : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[MII.scala 53:25]
+    reg BitCounter : UInt<7>, clock with :
+      reset => (reset, UInt<7>("h0")) @[MII.scala 56:27]
+    node EndOp = eq(BitCounter, UInt<6>("h3f")) @[MII.scala 57:26]
+    reg InProgress : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[MII.scala 60:27]
+    reg InProgress_q_0 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn : @[Reg.scala 36:18]
+      InProgress_q_0 <= InProgress @[Reg.scala 36:22]
+    reg InProgress_q_1 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn : @[Reg.scala 36:18]
+      InProgress_q_1 <= InProgress_q_0 @[Reg.scala 36:22]
+    reg InProgress_q_2 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn : @[Reg.scala 36:18]
+      InProgress_q_2 <= InProgress_q_1 @[Reg.scala 36:22]
+    node _EndBusy_T = not(InProgress_q_1) @[MII.scala 62:32]
+    node _EndBusy_T_1 = and(_EndBusy_T, InProgress_q_2) @[MII.scala 62:49]
+    reg EndBusy_r : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when UInt<1>("h1") : @[Reg.scala 36:18]
+      EndBusy_r <= _EndBusy_T_1 @[Reg.scala 36:22]
+    reg EndBusy : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when UInt<1>("h1") : @[Reg.scala 36:18]
+      EndBusy <= EndBusy_r @[Reg.scala 36:22]
+    reg WriteOp : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[MII.scala 64:27]
+    io.mdc <= mdc @[MII.scala 69:10]
+    io.LinkFail <= LinkFail @[MII.scala 70:15]
+    io.Prsd <= Prsd @[MII.scala 71:11]
+    node _TempDivider_T = lt(io.Divider, UInt<2>("h2")) @[MII.scala 82:39]
+    node TempDivider = mux(_TempDivider_T, UInt<2>("h2"), io.Divider) @[MII.scala 82:26]
+    node _CounterPreset_T = shr(TempDivider, 1) @[MII.scala 83:37]
+    node _CounterPreset_T_1 = sub(_CounterPreset_T, UInt<1>("h1")) @[MII.scala 83:44]
+    node CounterPreset = tail(_CounterPreset_T_1, 1) @[MII.scala 83:44]
+    node _T = eq(Counter, UInt<1>("h0")) @[MII.scala 85:17]
+    when _T : @[MII.scala 85:27]
+      node _mdc_T = not(mdc) @[MII.scala 86:12]
+      mdc <= _mdc_T @[MII.scala 86:9]
+      Counter <= CounterPreset @[MII.scala 87:13]
+    else :
+      node _Counter_T = sub(Counter, UInt<1>("h1")) @[MII.scala 89:24]
+      node _Counter_T_1 = tail(_Counter_T, 1) @[MII.scala 89:24]
+      Counter <= _Counter_T_1 @[MII.scala 89:13]
+    node _LatchByte0_T = not(WriteOp) @[MII.scala 97:47]
+    node _LatchByte0_T_1 = and(InProgress, _LatchByte0_T) @[MII.scala 97:45]
+    node _LatchByte0_T_2 = eq(BitCounter, UInt<6>("h3f")) @[MII.scala 97:69]
+    node _LatchByte0_T_3 = and(_LatchByte0_T_1, _LatchByte0_T_2) @[MII.scala 97:56]
+    reg LatchByte0_r : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn : @[Reg.scala 36:18]
+      LatchByte0_r <= _LatchByte0_T_3 @[Reg.scala 36:22]
+    reg LatchByte0 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn : @[Reg.scala 36:18]
+      LatchByte0 <= LatchByte0_r @[Reg.scala 36:22]
+    node _LatchByte1_T = not(WriteOp) @[MII.scala 98:47]
+    node _LatchByte1_T_1 = and(InProgress, _LatchByte1_T) @[MII.scala 98:45]
+    node _LatchByte1_T_2 = eq(BitCounter, UInt<6>("h37")) @[MII.scala 98:69]
+    node _LatchByte1_T_3 = and(_LatchByte1_T_1, _LatchByte1_T_2) @[MII.scala 98:56]
+    reg LatchByte1_r : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn : @[Reg.scala 36:18]
+      LatchByte1_r <= _LatchByte1_T_3 @[Reg.scala 36:22]
+    reg LatchByte1 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn : @[Reg.scala 36:18]
+      LatchByte1 <= LatchByte1_r @[Reg.scala 36:22]
+    node _ByteSelect_0_T = eq(BitCounter, UInt<1>("h0")) @[MII.scala 100:58]
+    node _ByteSelect_0_T_1 = and(io.NoPre, _ByteSelect_0_T) @[MII.scala 100:44]
+    node _ByteSelect_0_T_2 = not(io.NoPre) @[MII.scala 100:71]
+    node _ByteSelect_0_T_3 = eq(BitCounter, UInt<6>("h20")) @[MII.scala 100:95]
+    node _ByteSelect_0_T_4 = and(_ByteSelect_0_T_2, _ByteSelect_0_T_3) @[MII.scala 100:81]
+    node _ByteSelect_0_T_5 = or(_ByteSelect_0_T_1, _ByteSelect_0_T_4) @[MII.scala 100:68]
+    node _ByteSelect_0_T_6 = and(InProgress, _ByteSelect_0_T_5) @[MII.scala 100:31]
+    ByteSelect[0] <= _ByteSelect_0_T_6 @[MII.scala 100:17]
+    node _ByteSelect_1_T = eq(BitCounter, UInt<6>("h28")) @[MII.scala 101:45]
+    node _ByteSelect_1_T_1 = and(InProgress, _ByteSelect_1_T) @[MII.scala 101:31]
+    ByteSelect[1] <= _ByteSelect_1_T_1 @[MII.scala 101:17]
+    node _ByteSelect_2_T = and(InProgress, WriteOp) @[MII.scala 102:31]
+    node _ByteSelect_2_T_1 = eq(BitCounter, UInt<6>("h30")) @[MII.scala 102:55]
+    node _ByteSelect_2_T_2 = and(_ByteSelect_2_T, _ByteSelect_2_T_1) @[MII.scala 102:41]
+    ByteSelect[2] <= _ByteSelect_2_T_2 @[MII.scala 102:17]
+    node _ByteSelect_3_T = and(InProgress, WriteOp) @[MII.scala 103:31]
+    node _ByteSelect_3_T_1 = eq(BitCounter, UInt<6>("h38")) @[MII.scala 103:55]
+    node _ByteSelect_3_T_2 = and(_ByteSelect_3_T, _ByteSelect_3_T_1) @[MII.scala 103:41]
+    ByteSelect[3] <= _ByteSelect_3_T_2 @[MII.scala 103:17]
+    when mdcEn_n : @[MII.scala 105:16]
+      node _T_1 = or(ByteSelect[0], ByteSelect[1]) @[MII.scala 106:29]
+      node _T_2 = or(_T_1, ByteSelect[2]) @[MII.scala 106:29]
+      node _T_3 = or(_T_2, ByteSelect[3]) @[MII.scala 106:29]
+      when _T_3 : @[MII.scala 106:34]
+        node _ShiftReg_T = not(WriteOp) @[MII.scala 108:44]
+        node _ShiftReg_T_1 = bits(io.Fiad, 4, 1) @[MII.scala 108:70]
+        node ShiftReg_lo = cat(WriteOp, _ShiftReg_T_1) @[Cat.scala 33:92]
+        node ShiftReg_hi = cat(UInt<2>("h1"), _ShiftReg_T) @[Cat.scala 33:92]
+        node _ShiftReg_T_2 = cat(ShiftReg_hi, ShiftReg_lo) @[Cat.scala 33:92]
+        node _ShiftReg_T_3 = bits(io.Fiad, 0, 0) @[MII.scala 109:45]
+        node _ShiftReg_T_4 = bits(io.Rgad, 4, 0) @[MII.scala 109:57]
+        node ShiftReg_hi_1 = cat(_ShiftReg_T_3, _ShiftReg_T_4) @[Cat.scala 33:92]
+        node _ShiftReg_T_5 = cat(ShiftReg_hi_1, UInt<2>("h2")) @[Cat.scala 33:92]
+        node _ShiftReg_T_6 = bits(io.CtrlData, 15, 8) @[MII.scala 110:37]
+        node _ShiftReg_T_7 = bits(io.CtrlData, 7, 0) @[MII.scala 111:37]
+        node _ShiftReg_T_8 = mux(ByteSelect[0], _ShiftReg_T_2, UInt<1>("h0")) @[Mux.scala 27:73]
+        node _ShiftReg_T_9 = mux(ByteSelect[1], _ShiftReg_T_5, UInt<1>("h0")) @[Mux.scala 27:73]
+        node _ShiftReg_T_10 = mux(ByteSelect[2], _ShiftReg_T_6, UInt<1>("h0")) @[Mux.scala 27:73]
+        node _ShiftReg_T_11 = mux(ByteSelect[3], _ShiftReg_T_7, UInt<1>("h0")) @[Mux.scala 27:73]
+        node _ShiftReg_T_12 = or(_ShiftReg_T_8, _ShiftReg_T_9) @[Mux.scala 27:73]
+        node _ShiftReg_T_13 = or(_ShiftReg_T_12, _ShiftReg_T_10) @[Mux.scala 27:73]
+        node _ShiftReg_T_14 = or(_ShiftReg_T_13, _ShiftReg_T_11) @[Mux.scala 27:73]
+        wire _ShiftReg_WIRE : UInt<8> @[Mux.scala 27:73]
+        _ShiftReg_WIRE <= _ShiftReg_T_14 @[Mux.scala 27:73]
+        ShiftReg <= _ShiftReg_WIRE @[MII.scala 107:16]
+      else :
+        node _ShiftReg_T_15 = bits(ShiftReg, 6, 0) @[MII.scala 114:31]
+        node _ShiftReg_T_16 = cat(_ShiftReg_T_15, io.mdi) @[Cat.scala 33:92]
+        ShiftReg <= _ShiftReg_T_16 @[MII.scala 114:16]
+        when LatchByte0 : @[MII.scala 115:23]
+          node _Prsd_T = bits(Prsd, 15, 8) @[MII.scala 116:25]
+          node _Prsd_T_1 = bits(ShiftReg, 6, 0) @[MII.scala 116:41]
+          node Prsd_hi = cat(_Prsd_T, _Prsd_T_1) @[Cat.scala 33:92]
+          node _Prsd_T_2 = cat(Prsd_hi, io.mdi) @[Cat.scala 33:92]
+          Prsd <= _Prsd_T_2 @[MII.scala 116:14]
+          node _T_4 = eq(io.Rgad, UInt<1>("h1")) @[MII.scala 117:22]
+          when _T_4 : @[MII.scala 117:30]
+            node _LinkFail_T = bits(ShiftReg, 1, 1) @[MII.scala 118:40]
+            node _LinkFail_T_1 = not(_LinkFail_T) @[MII.scala 118:23]
+            LinkFail <= _LinkFail_T_1 @[MII.scala 118:20]
+        else :
+          when LatchByte1 : @[MII.scala 120:30]
+            node _Prsd_T_3 = bits(ShiftReg, 6, 0) @[MII.scala 121:29]
+            node _Prsd_T_4 = bits(Prsd, 7, 0) @[MII.scala 121:48]
+            node Prsd_hi_1 = cat(_Prsd_T_3, io.mdi) @[Cat.scala 33:92]
+            node _Prsd_T_5 = cat(Prsd_hi_1, _Prsd_T_4) @[Cat.scala 33:92]
+            Prsd <= _Prsd_T_5 @[MII.scala 121:14]
+    node _SerialEn_T = and(WriteOp, InProgress) @[MII.scala 131:29]
+    node _SerialEn_T_1 = gt(BitCounter, UInt<5>("h1f")) @[MII.scala 131:57]
+    node _SerialEn_T_2 = eq(BitCounter, UInt<1>("h0")) @[MII.scala 131:81]
+    node _SerialEn_T_3 = and(_SerialEn_T_2, io.NoPre) @[MII.scala 131:91]
+    node _SerialEn_T_4 = or(_SerialEn_T_1, _SerialEn_T_3) @[MII.scala 131:64]
+    node _SerialEn_T_5 = and(_SerialEn_T, _SerialEn_T_4) @[MII.scala 131:42]
+    node _SerialEn_T_6 = not(WriteOp) @[MII.scala 132:20]
+    node _SerialEn_T_7 = and(_SerialEn_T_6, InProgress) @[MII.scala 132:29]
+    node _SerialEn_T_8 = gt(BitCounter, UInt<5>("h1f")) @[MII.scala 132:58]
+    node _SerialEn_T_9 = lt(BitCounter, UInt<6>("h2e")) @[MII.scala 132:78]
+    node _SerialEn_T_10 = and(_SerialEn_T_8, _SerialEn_T_9) @[MII.scala 132:65]
+    node _SerialEn_T_11 = eq(BitCounter, UInt<1>("h0")) @[MII.scala 132:104]
+    node _SerialEn_T_12 = and(_SerialEn_T_11, io.NoPre) @[MII.scala 132:114]
+    node _SerialEn_T_13 = or(_SerialEn_T_10, _SerialEn_T_12) @[MII.scala 132:87]
+    node _SerialEn_T_14 = and(_SerialEn_T_7, _SerialEn_T_13) @[MII.scala 132:42]
+    node SerialEn = or(_SerialEn_T_5, _SerialEn_T_14) @[MII.scala 131:107]
+    node _mdoEn_T = lt(BitCounter, UInt<6>("h20")) @[MII.scala 134:66]
+    node _mdoEn_T_1 = and(InProgress, _mdoEn_T) @[MII.scala 134:54]
+    node _mdoEn_T_2 = or(SerialEn, _mdoEn_T_1) @[MII.scala 134:40]
+    reg mdoEn_r : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn_n : @[Reg.scala 36:18]
+      mdoEn_r <= _mdoEn_T_2 @[Reg.scala 36:22]
+    reg mdoEn_r_1 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn_n : @[Reg.scala 36:18]
+      mdoEn_r_1 <= mdoEn_r @[Reg.scala 36:22]
+    reg mdoEn : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn_n : @[Reg.scala 36:18]
+      mdoEn <= mdoEn_r_1 @[Reg.scala 36:22]
+    node _mdo_2d_T = not(SerialEn) @[MII.scala 135:27]
+    node _mdo_2d_T_1 = lt(BitCounter, UInt<6>("h20")) @[MII.scala 135:49]
+    node _mdo_2d_T_2 = and(_mdo_2d_T, _mdo_2d_T_1) @[MII.scala 135:37]
+    reg mdo_2d : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn_n : @[Reg.scala 36:18]
+      mdo_2d <= _mdo_2d_T_2 @[Reg.scala 36:22]
+    node _mdo_d_T = bits(ShiftReg, 7, 7) @[MII.scala 136:43]
+    node _mdo_d_T_1 = or(_mdo_d_T, mdo_2d) @[MII.scala 136:47]
+    reg mdo_d : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn_n : @[Reg.scala 36:18]
+      mdo_d <= _mdo_d_T_1 @[Reg.scala 36:22]
+    reg mdo : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn_n : @[Reg.scala 36:18]
+      mdo <= mdo_d @[Reg.scala 36:22]
+    io.mdo <= mdo @[MII.scala 138:10]
+    io.mdoEn <= mdoEn @[MII.scala 139:12]
+    reg WCtrlData_q_0 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when UInt<1>("h1") : @[Reg.scala 36:18]
+      WCtrlData_q_0 <= io.WCtrlData @[Reg.scala 36:22]
+    reg WCtrlData_q_1 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when UInt<1>("h1") : @[Reg.scala 36:18]
+      WCtrlData_q_1 <= WCtrlData_q_0 @[Reg.scala 36:22]
+    reg WCtrlData_q_2 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when UInt<1>("h1") : @[Reg.scala 36:18]
+      WCtrlData_q_2 <= WCtrlData_q_1 @[Reg.scala 36:22]
+    reg WCtrlDataStart : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[MII.scala 147:31]
+    reg WCtrlDataStart_q_0 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn : @[Reg.scala 36:18]
+      WCtrlDataStart_q_0 <= WCtrlDataStart @[Reg.scala 36:22]
+    reg WCtrlDataStart_q_1 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn : @[Reg.scala 36:18]
+      WCtrlDataStart_q_1 <= WCtrlDataStart_q_0 @[Reg.scala 36:22]
+    node _WriteDataOp_T = not(WCtrlDataStart_q_1) @[MII.scala 149:44]
+    node WriteDataOp = and(WCtrlDataStart_q_0, _WriteDataOp_T) @[MII.scala 149:42]
+    io.WCtrlDataStart <= WCtrlDataStart @[MII.scala 150:21]
+    wire StartOp : UInt<1> @[MII.scala 156:21]
+    when EndBusy : @[MII.scala 160:18]
+      WCtrlDataStart <= UInt<1>("h0") @[MII.scala 161:20]
+    else :
+      node _T_5 = not(WCtrlData_q_2) @[MII.scala 162:33]
+      node _T_6 = and(WCtrlData_q_1, _T_5) @[MII.scala 162:31]
+      when _T_6 : @[MII.scala 162:50]
+        WCtrlDataStart <= UInt<1>("h1") @[MII.scala 163:20]
+    node _WCtrlDataStart_q0_T = not(EndBusy) @[MII.scala 167:62]
+    reg WCtrlDataStart_q0 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when _WCtrlDataStart_q0_T : @[Reg.scala 36:18]
+      WCtrlDataStart_q0 <= WCtrlDataStart @[Reg.scala 36:22]
+    node _UpdateMIIRX_DATAReg_T = not(WCtrlDataStart_q0) @[MII.scala 168:47]
+    node _UpdateMIIRX_DATAReg_T_1 = and(EndBusy, _UpdateMIIRX_DATAReg_T) @[MII.scala 168:45]
+    reg UpdateMIIRX_DATAReg : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[MII.scala 168:36]
+    UpdateMIIRX_DATAReg <= _UpdateMIIRX_DATAReg_T_1 @[MII.scala 168:36]
+    io.UpdateMIIRX_DATAReg <= UpdateMIIRX_DATAReg @[MII.scala 169:26]
+    reg RStat_q_0 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when UInt<1>("h1") : @[Reg.scala 36:18]
+      RStat_q_0 <= io.RStat @[Reg.scala 36:22]
+    reg RStat_q_1 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when UInt<1>("h1") : @[Reg.scala 36:18]
+      RStat_q_1 <= RStat_q_0 @[Reg.scala 36:22]
+    reg RStat_q_2 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when UInt<1>("h1") : @[Reg.scala 36:18]
+      RStat_q_2 <= RStat_q_1 @[Reg.scala 36:22]
+    reg RStatStart : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[MII.scala 174:27]
+    reg RStatStart_q_0 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn : @[Reg.scala 36:18]
+      RStatStart_q_0 <= RStatStart @[Reg.scala 36:22]
+    reg RStatStart_q_1 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn : @[Reg.scala 36:18]
+      RStatStart_q_1 <= RStatStart_q_0 @[Reg.scala 36:22]
+    node _ReadStatusOp_T = not(RStatStart_q_1) @[MII.scala 176:44]
+    node ReadStatusOp = and(RStatStart_q_0, _ReadStatusOp_T) @[MII.scala 176:42]
+    io.RStatStart <= RStatStart @[MII.scala 177:17]
+    when EndBusy : @[MII.scala 179:18]
+      RStatStart <= UInt<1>("h0") @[MII.scala 180:16]
+    else :
+      node _T_7 = not(RStat_q_2) @[MII.scala 181:28]
+      node _T_8 = and(RStat_q_1, _T_7) @[MII.scala 181:26]
+      when _T_8 : @[MII.scala 181:40]
+        RStatStart <= UInt<1>("h1") @[MII.scala 182:16]
+    when mdcEn : @[MII.scala 188:14]
+      when StartOp : @[MII.scala 189:19]
+        InProgress <= UInt<1>("h1") @[MII.scala 190:18]
+      else :
+        when EndOp : @[MII.scala 191:24]
+          InProgress <= UInt<1>("h0") @[MII.scala 192:18]
+    reg ScanStat_q_0 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when UInt<1>("h1") : @[Reg.scala 36:18]
+      ScanStat_q_0 <= io.ScanStat @[Reg.scala 36:22]
+    reg ScanStat_q_1 : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when UInt<1>("h1") : @[Reg.scala 36:18]
+      ScanStat_q_1 <= ScanStat_q_0 @[Reg.scala 36:22]
+    reg SyncStatmdcEn : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20]
+    when mdcEn : @[Reg.scala 36:18]
+      SyncStatmdcEn <= ScanStat_q_1 @[Reg.scala 36:22]
+    node _ScanStatusOp_T = not(InProgress) @[MII.scala 200:44]
+    node _ScanStatusOp_T_1 = and(SyncStatmdcEn, _ScanStatusOp_T) @[MII.scala 200:42]
+    node _ScanStatusOp_T_2 = not(InProgress_q_0) @[MII.scala 200:58]
+    node _ScanStatusOp_T_3 = and(_ScanStatusOp_T_1, _ScanStatusOp_T_2) @[MII.scala 200:56]
+    node _ScanStatusOp_T_4 = not(InProgress_q_1) @[MII.scala 200:77]
+    node ScanStatusOp = and(_ScanStatusOp_T_3, _ScanStatusOp_T_4) @[MII.scala 200:75]
+    reg Nvalid : UInt<1>, clock with :
+      reset => (reset, UInt<1>("h0")) @[MII.scala 203:23]
+    io.Nvalid <= Nvalid @[MII.scala 204:13]
+    node _T_9 = not(InProgress_q_1) @[MII.scala 206:9]
+    node _T_10 = and(_T_9, InProgress_q_2) @[MII.scala 206:26]
+    when _T_10 : @[MII.scala 206:46]
+      Nvalid <= UInt<1>("h0") @[MII.scala 207:12]
+    else :
+      node _T_11 = not(SyncStatmdcEn) @[MII.scala 208:32]
+      node _T_12 = and(ScanStat_q_1, _T_11) @[MII.scala 208:30]
+      when _T_12 : @[MII.scala 208:48]
+        Nvalid <= UInt<1>("h1") @[MII.scala 209:12]
+    when mdcEn : @[MII.scala 215:14]
+      when StartOp : @[MII.scala 216:19]
+        node _T_13 = not(InProgress) @[MII.scala 217:13]
+        when _T_13 : @[MII.scala 217:26]
+          node _WriteOp_T = mux(WriteDataOp, UInt<1>("h1"), UInt<1>("h0")) @[MII.scala 218:23]
+          WriteOp <= _WriteOp_T @[MII.scala 218:17]
+      else :
+        when EndOp : @[MII.scala 220:24]
+          WriteOp <= UInt<1>("h0") @[MII.scala 221:15]
+    when mdcEn : @[MII.scala 226:16]
+      when InProgress : @[MII.scala 227:24]
+        node _T_14 = eq(BitCounter, UInt<1>("h0")) @[MII.scala 228:35]
+        node _T_15 = and(io.NoPre, _T_14) @[MII.scala 228:22]
+        when _T_15 : @[MII.scala 228:45]
+          BitCounter <= UInt<6>("h21") @[MII.scala 229:20]
+        else :
+          node _BitCounter_T = add(BitCounter, UInt<1>("h1")) @[MII.scala 231:34]
+          node _BitCounter_T_1 = tail(_BitCounter_T, 1) @[MII.scala 231:34]
+          BitCounter <= _BitCounter_T_1 @[MII.scala 231:20]
+      else :
+        BitCounter <= UInt<1>("h0") @[MII.scala 234:18]
+    node _StartOp_T = or(WriteDataOp, ReadStatusOp) @[MII.scala 239:26]
+    node _StartOp_T_1 = or(_StartOp_T, ScanStatusOp) @[MII.scala 239:41]
+    StartOp <= _StartOp_T_1 @[MII.scala 239:11]
+    node _io_Busy_T = or(io.WCtrlData, WCtrlDataStart) @[MII.scala 240:27]
+    node _io_Busy_T_1 = or(_io_Busy_T, io.RStat) @[MII.scala 240:44]
+    node _io_Busy_T_2 = or(_io_Busy_T_1, RStatStart) @[MII.scala 240:55]
+    node _io_Busy_T_3 = or(_io_Busy_T_2, SyncStatmdcEn) @[MII.scala 240:68]
+    node _io_Busy_T_4 = or(_io_Busy_T_3, EndBusy) @[MII.scala 240:84]
+    node _io_Busy_T_5 = or(_io_Busy_T_4, InProgress) @[MII.scala 240:94]
+    node _io_Busy_T_6 = or(_io_Busy_T_5, InProgress_q_2) @[MII.scala 240:107]
+    node _io_Busy_T_7 = or(_io_Busy_T_6, Nvalid) @[MII.scala 240:125]
+    io.Busy <= _io_Busy_T_7 @[MII.scala 240:11]
+

generated/MIIM.v

@@ -0,0 +1,542 @@
+module MIIM(
+  input         clock,
+  input         reset,
+  input         io_mdi,
+  output        io_mdc,
+  output        io_mdo,
+  output        io_mdoEn,
+  input  [7:0]  io_Divider,
+  input         io_NoPre,
+  input         io_WCtrlData,
+  input  [15:0] io_CtrlData,
+  input  [4:0]  io_Fiad,
+  input  [4:0]  io_Rgad,
+  input         io_RStat,
+  input         io_ScanStat,
+  output        io_Busy,
+  output        io_LinkFail,
+  output        io_Nvalid,
+  output [15:0] io_Prsd,
+  output        io_WCtrlDataStart,
+  output        io_RStatStart,
+  output        io_UpdateMIIRX_DATAReg
+);
+`ifdef RANDOMIZE_REG_INIT
+  reg [31:0] _RAND_0;
+  reg [31:0] _RAND_1;
+  reg [31:0] _RAND_2;
+  reg [31:0] _RAND_3;
+  reg [31:0] _RAND_4;
+  reg [31:0] _RAND_5;
+  reg [31:0] _RAND_6;
+  reg [31:0] _RAND_7;
+  reg [31:0] _RAND_8;
+  reg [31:0] _RAND_9;
+  reg [31:0] _RAND_10;
+  reg [31:0] _RAND_11;
+  reg [31:0] _RAND_12;
+  reg [31:0] _RAND_13;
+  reg [31:0] _RAND_14;
+  reg [31:0] _RAND_15;
+  reg [31:0] _RAND_16;
+  reg [31:0] _RAND_17;
+  reg [31:0] _RAND_18;
+  reg [31:0] _RAND_19;
+  reg [31:0] _RAND_20;
+  reg [31:0] _RAND_21;
+  reg [31:0] _RAND_22;
+  reg [31:0] _RAND_23;
+  reg [31:0] _RAND_24;
+  reg [31:0] _RAND_25;
+  reg [31:0] _RAND_26;
+  reg [31:0] _RAND_27;
+  reg [31:0] _RAND_28;
+  reg [31:0] _RAND_29;
+  reg [31:0] _RAND_30;
+  reg [31:0] _RAND_31;
+  reg [31:0] _RAND_32;
+  reg [31:0] _RAND_33;
+  reg [31:0] _RAND_34;
+  reg [31:0] _RAND_35;
+  reg [31:0] _RAND_36;
+  reg [31:0] _RAND_37;
+  reg [31:0] _RAND_38;
+  reg [31:0] _RAND_39;
+  reg [31:0] _RAND_40;
+`endif // RANDOMIZE_REG_INIT
+  reg [7:0] Counter; // @[MII.scala 46:25]
+  reg  mdc; // @[MII.scala 47:20]
+  wire  _mdcEn_T = Counter == 8'h0; // @[MII.scala 48:27]
+  wire  _mdcEn_T_1 = ~mdc; // @[MII.scala 48:38]
+  wire  mdcEn = Counter == 8'h0 & ~mdc; // @[MII.scala 48:36]
+  wire  mdcEn_n = _mdcEn_T & mdc; // @[MII.scala 49:36]
+  reg [7:0] ShiftReg; // @[MII.scala 51:25]
+  reg [15:0] Prsd; // @[MII.scala 52:25]
+  reg  LinkFail; // @[MII.scala 53:25]
+  reg [6:0] BitCounter; // @[MII.scala 56:27]
+  wire  EndOp = BitCounter == 7'h3f; // @[MII.scala 57:26]
+  reg  InProgress; // @[MII.scala 60:27]
+  reg  InProgress_q_0; // @[Reg.scala 35:20]
+  reg  InProgress_q_1; // @[Reg.scala 35:20]
+  reg  InProgress_q_2; // @[Reg.scala 35:20]
+  wire  _EndBusy_T = ~InProgress_q_1; // @[MII.scala 62:32]
+  wire  _EndBusy_T_1 = ~InProgress_q_1 & InProgress_q_2; // @[MII.scala 62:49]
+  reg  EndBusy_r; // @[Reg.scala 35:20]
+  reg  EndBusy; // @[Reg.scala 35:20]
+  reg  WriteOp; // @[MII.scala 64:27]
+  wire [7:0] TempDivider = io_Divider < 8'h2 ? 8'h2 : io_Divider; // @[MII.scala 82:26]
+  wire [6:0] CounterPreset = TempDivider[7:1] - 7'h1; // @[MII.scala 83:44]
+  wire [7:0] _Counter_T_1 = Counter - 8'h1; // @[MII.scala 89:24]
+  wire  _LatchByte0_T = ~WriteOp; // @[MII.scala 97:47]
+  wire  _LatchByte0_T_1 = InProgress & ~WriteOp; // @[MII.scala 97:45]
+  wire  _LatchByte0_T_3 = InProgress & ~WriteOp & EndOp; // @[MII.scala 97:56]
+  reg  LatchByte0_r; // @[Reg.scala 35:20]
+  reg  LatchByte0; // @[Reg.scala 35:20]
+  wire  _LatchByte1_T_3 = _LatchByte0_T_1 & BitCounter == 7'h37; // @[MII.scala 98:56]
+  reg  LatchByte1_r; // @[Reg.scala 35:20]
+  reg  LatchByte1; // @[Reg.scala 35:20]
+  wire  _ByteSelect_0_T = BitCounter == 7'h0; // @[MII.scala 100:58]
+  wire  _ByteSelect_0_T_1 = io_NoPre & BitCounter == 7'h0; // @[MII.scala 100:44]
+  wire  ByteSelect_0 = InProgress & (io_NoPre & BitCounter == 7'h0 | ~io_NoPre & BitCounter == 7'h20); // @[MII.scala 100:31]
+  wire  ByteSelect_1 = InProgress & BitCounter == 7'h28; // @[MII.scala 101:31]
+  wire  _ByteSelect_2_T = InProgress & WriteOp; // @[MII.scala 102:31]
+  wire  ByteSelect_2 = InProgress & WriteOp & BitCounter == 7'h30; // @[MII.scala 102:41]
+  wire  ByteSelect_3 = _ByteSelect_2_T & BitCounter == 7'h38; // @[MII.scala 103:41]
+  wire [7:0] _ShiftReg_T_2 = {2'h1,_LatchByte0_T,WriteOp,io_Fiad[4:1]}; // @[Cat.scala 33:92]
+  wire [7:0] _ShiftReg_T_5 = {io_Fiad[0],io_Rgad,2'h2}; // @[Cat.scala 33:92]
+  wire [7:0] _ShiftReg_T_8 = ByteSelect_0 ? _ShiftReg_T_2 : 8'h0; // @[Mux.scala 27:73]
+  wire [7:0] _ShiftReg_T_9 = ByteSelect_1 ? _ShiftReg_T_5 : 8'h0; // @[Mux.scala 27:73]
+  wire [7:0] _ShiftReg_T_10 = ByteSelect_2 ? io_CtrlData[15:8] : 8'h0; // @[Mux.scala 27:73]
+  wire [7:0] _ShiftReg_T_11 = ByteSelect_3 ? io_CtrlData[7:0] : 8'h0; // @[Mux.scala 27:73]
+  wire [7:0] _ShiftReg_T_12 = _ShiftReg_T_8 | _ShiftReg_T_9; // @[Mux.scala 27:73]
+  wire [7:0] _ShiftReg_T_13 = _ShiftReg_T_12 | _ShiftReg_T_10; // @[Mux.scala 27:73]
+  wire [7:0] _ShiftReg_T_14 = _ShiftReg_T_13 | _ShiftReg_T_11; // @[Mux.scala 27:73]
+  wire [7:0] _ShiftReg_T_16 = {ShiftReg[6:0],io_mdi}; // @[Cat.scala 33:92]
+  wire [15:0] _Prsd_T_2 = {Prsd[15:8],ShiftReg[6:0],io_mdi}; // @[Cat.scala 33:92]
+  wire  _GEN_11 = io_Rgad == 5'h1 ? ~ShiftReg[1] : LinkFail; // @[MII.scala 117:30 118:20 53:25]
+  wire [15:0] _Prsd_T_5 = {ShiftReg[6:0],io_mdi,Prsd[7:0]}; // @[Cat.scala 33:92]
+  wire [15:0] _GEN_12 = LatchByte1 ? _Prsd_T_5 : Prsd; // @[MII.scala 120:30 121:14 52:25]
+  wire  _SerialEn_T_1 = BitCounter > 7'h1f; // @[MII.scala 131:57]
+  wire  _SerialEn_T_3 = _ByteSelect_0_T & io_NoPre; // @[MII.scala 131:91]
+  wire  _SerialEn_T_14 = _LatchByte0_T & InProgress & (_SerialEn_T_1 & BitCounter < 7'h2e | _SerialEn_T_3); // @[MII.scala 132:42]
+  wire  SerialEn = WriteOp & InProgress & (BitCounter > 7'h1f | _ByteSelect_0_T & io_NoPre) | _SerialEn_T_14; // @[MII.scala 131:107]
+  wire  _mdoEn_T = BitCounter < 7'h20; // @[MII.scala 134:66]
+  wire  _mdoEn_T_2 = SerialEn | InProgress & BitCounter < 7'h20; // @[MII.scala 134:40]
+  reg  mdoEn_r; // @[Reg.scala 35:20]
+  reg  mdoEn_r_1; // @[Reg.scala 35:20]
+  reg  mdoEn; // @[Reg.scala 35:20]
+  wire  _mdo_2d_T_2 = ~SerialEn & _mdoEn_T; // @[MII.scala 135:37]
+  reg  mdo_2d; // @[Reg.scala 35:20]
+  wire  _mdo_d_T_1 = ShiftReg[7] | mdo_2d; // @[MII.scala 136:47]
+  reg  mdo_d; // @[Reg.scala 35:20]
+  reg  mdo; // @[Reg.scala 35:20]
+  reg  WCtrlData_q_0; // @[Reg.scala 35:20]
+  reg  WCtrlData_q_1; // @[Reg.scala 35:20]
+  reg  WCtrlData_q_2; // @[Reg.scala 35:20]
+  reg  WCtrlDataStart; // @[MII.scala 147:31]
+  reg  WCtrlDataStart_q_0; // @[Reg.scala 35:20]
+  reg  WCtrlDataStart_q_1; // @[Reg.scala 35:20]
+  wire  WriteDataOp = WCtrlDataStart_q_0 & ~WCtrlDataStart_q_1; // @[MII.scala 149:42]
+  wire  _GEN_32 = WCtrlData_q_1 & ~WCtrlData_q_2 | WCtrlDataStart; // @[MII.scala 162:50 163:20 147:31]
+  wire  _WCtrlDataStart_q0_T = ~EndBusy; // @[MII.scala 167:62]
+  reg  WCtrlDataStart_q0; // @[Reg.scala 35:20]
+  reg  UpdateMIIRX_DATAReg; // @[MII.scala 168:36]
+  reg  RStat_q_0; // @[Reg.scala 35:20]
+  reg  RStat_q_1; // @[Reg.scala 35:20]
+  reg  RStat_q_2; // @[Reg.scala 35:20]
+  reg  RStatStart; // @[MII.scala 174:27]
+  reg  RStatStart_q_0; // @[Reg.scala 35:20]
+  reg  RStatStart_q_1; // @[Reg.scala 35:20]
+  wire  ReadStatusOp = RStatStart_q_0 & ~RStatStart_q_1; // @[MII.scala 176:42]
+  wire  _GEN_40 = RStat_q_1 & ~RStat_q_2 | RStatStart; // @[MII.scala 181:40 182:16 174:27]
+  wire  _GEN_42 = EndOp ? 1'h0 : InProgress; // @[MII.scala 191:24 192:18 60:27]
+  reg  SyncStatmdcEn; // @[Reg.scala 35:20]
+  wire  _ScanStatusOp_T = ~InProgress; // @[MII.scala 200:44]
+  wire  ScanStatusOp = SyncStatmdcEn & ~InProgress & ~InProgress_q_0 & _EndBusy_T; // @[MII.scala 200:75]
+  wire  StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp; // @[MII.scala 239:41]
+  wire  _GEN_43 = StartOp | _GEN_42; // @[MII.scala 189:19 190:18]
+  reg  ScanStat_q_0; // @[Reg.scala 35:20]
+  reg  ScanStat_q_1; // @[Reg.scala 35:20]
+  reg  Nvalid; // @[MII.scala 203:23]
+  wire  _GEN_48 = ScanStat_q_1 & ~SyncStatmdcEn | Nvalid; // @[MII.scala 208:48 209:12 203:23]
+  wire [6:0] _BitCounter_T_1 = BitCounter + 7'h1; // @[MII.scala 231:34]
+  assign io_mdc = mdc; // @[MII.scala 69:10]
+  assign io_mdo = mdo; // @[MII.scala 138:10]
+  assign io_mdoEn = mdoEn; // @[MII.scala 139:12]
+  assign io_Busy = io_WCtrlData | WCtrlDataStart | io_RStat | RStatStart | SyncStatmdcEn | EndBusy | InProgress |
+    InProgress_q_2 | Nvalid; // @[MII.scala 240:125]
+  assign io_LinkFail = LinkFail; // @[MII.scala 70:15]
+  assign io_Nvalid = Nvalid; // @[MII.scala 204:13]
+  assign io_Prsd = Prsd; // @[MII.scala 71:11]
+  assign io_WCtrlDataStart = WCtrlDataStart; // @[MII.scala 150:21]
+  assign io_RStatStart = RStatStart; // @[MII.scala 177:17]
+  assign io_UpdateMIIRX_DATAReg = UpdateMIIRX_DATAReg; // @[MII.scala 169:26]
+  always @(posedge clock) begin
+    if (reset) begin // @[MII.scala 46:25]
+      Counter <= 8'h1; // @[MII.scala 46:25]
+    end else if (_mdcEn_T) begin // @[MII.scala 85:27]
+      Counter <= {{1'd0}, CounterPreset}; // @[MII.scala 87:13]
+    end else begin
+      Counter <= _Counter_T_1; // @[MII.scala 89:13]
+    end
+    if (reset) begin // @[MII.scala 47:20]
+      mdc <= 1'h0; // @[MII.scala 47:20]
+    end else if (_mdcEn_T) begin // @[MII.scala 85:27]
+      mdc <= _mdcEn_T_1; // @[MII.scala 86:9]
+    end
+    if (reset) begin // @[MII.scala 51:25]
+      ShiftReg <= 8'h0; // @[MII.scala 51:25]
+    end else if (mdcEn_n) begin // @[MII.scala 105:16]
+      if (ByteSelect_0 | ByteSelect_1 | ByteSelect_2 | ByteSelect_3) begin // @[MII.scala 106:34]
+        ShiftReg <= _ShiftReg_T_14; // @[MII.scala 107:16]
+      end else begin
+        ShiftReg <= _ShiftReg_T_16; // @[MII.scala 114:16]
+      end
+    end
+    if (reset) begin // @[MII.scala 52:25]
+      Prsd <= 16'h0; // @[MII.scala 52:25]
+    end else if (mdcEn_n) begin // @[MII.scala 105:16]
+      if (!(ByteSelect_0 | ByteSelect_1 | ByteSelect_2 | ByteSelect_3)) begin // @[MII.scala 106:34]
+        if (LatchByte0) begin // @[MII.scala 115:23]
+          Prsd <= _Prsd_T_2; // @[MII.scala 116:14]
+        end else begin
+          Prsd <= _GEN_12;
+        end
+      end
+    end
+    if (reset) begin // @[MII.scala 53:25]
+      LinkFail <= 1'h0; // @[MII.scala 53:25]
+    end else if (mdcEn_n) begin // @[MII.scala 105:16]
+      if (!(ByteSelect_0 | ByteSelect_1 | ByteSelect_2 | ByteSelect_3)) begin // @[MII.scala 106:34]
+        if (LatchByte0) begin // @[MII.scala 115:23]
+          LinkFail <= _GEN_11;
+        end
+      end
+    end
+    if (reset) begin // @[MII.scala 56:27]
+      BitCounter <= 7'h0; // @[MII.scala 56:27]
+    end else if (mdcEn) begin // @[MII.scala 226:16]
+      if (InProgress) begin // @[MII.scala 227:24]
+        if (_ByteSelect_0_T_1) begin // @[MII.scala 228:45]
+          BitCounter <= 7'h21; // @[MII.scala 229:20]
+        end else begin
+          BitCounter <= _BitCounter_T_1; // @[MII.scala 231:20]
+        end
+      end else begin
+        BitCounter <= 7'h0; // @[MII.scala 234:18]
+      end
+    end
+    if (reset) begin // @[MII.scala 60:27]
+      InProgress <= 1'h0; // @[MII.scala 60:27]
+    end else if (mdcEn) begin // @[MII.scala 188:14]
+      InProgress <= _GEN_43;
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      InProgress_q_0 <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn) begin // @[Reg.scala 36:18]
+      InProgress_q_0 <= InProgress; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      InProgress_q_1 <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn) begin // @[Reg.scala 36:18]
+      InProgress_q_1 <= InProgress_q_0; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      InProgress_q_2 <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn) begin // @[Reg.scala 36:18]
+      InProgress_q_2 <= InProgress_q_1; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      EndBusy_r <= 1'h0; // @[Reg.scala 35:20]
+    end else begin
+      EndBusy_r <= _EndBusy_T_1;
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      EndBusy <= 1'h0; // @[Reg.scala 35:20]
+    end else begin
+      EndBusy <= EndBusy_r;
+    end
+    if (reset) begin // @[MII.scala 64:27]
+      WriteOp <= 1'h0; // @[MII.scala 64:27]
+    end else if (mdcEn) begin // @[MII.scala 215:14]
+      if (StartOp) begin // @[MII.scala 216:19]
+        if (_ScanStatusOp_T) begin // @[MII.scala 217:26]
+          WriteOp <= WriteDataOp; // @[MII.scala 218:17]
+        end
+      end else if (EndOp) begin // @[MII.scala 220:24]
+        WriteOp <= 1'h0; // @[MII.scala 221:15]
+      end
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      LatchByte0_r <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn) begin // @[Reg.scala 36:18]
+      LatchByte0_r <= _LatchByte0_T_3; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      LatchByte0 <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn) begin // @[Reg.scala 36:18]
+      LatchByte0 <= LatchByte0_r; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      LatchByte1_r <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn) begin // @[Reg.scala 36:18]
+      LatchByte1_r <= _LatchByte1_T_3; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      LatchByte1 <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn) begin // @[Reg.scala 36:18]
+      LatchByte1 <= LatchByte1_r; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      mdoEn_r <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn_n) begin // @[Reg.scala 36:18]
+      mdoEn_r <= _mdoEn_T_2; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      mdoEn_r_1 <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn_n) begin // @[Reg.scala 36:18]
+      mdoEn_r_1 <= mdoEn_r; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      mdoEn <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn_n) begin // @[Reg.scala 36:18]
+      mdoEn <= mdoEn_r_1; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      mdo_2d <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn_n) begin // @[Reg.scala 36:18]
+      mdo_2d <= _mdo_2d_T_2; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      mdo_d <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn_n) begin // @[Reg.scala 36:18]
+      mdo_d <= _mdo_d_T_1; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      mdo <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn_n) begin // @[Reg.scala 36:18]
+      mdo <= mdo_d; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      WCtrlData_q_0 <= 1'h0; // @[Reg.scala 35:20]
+    end else begin
+      WCtrlData_q_0 <= io_WCtrlData;
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      WCtrlData_q_1 <= 1'h0; // @[Reg.scala 35:20]
+    end else begin
+      WCtrlData_q_1 <= WCtrlData_q_0;
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      WCtrlData_q_2 <= 1'h0; // @[Reg.scala 35:20]
+    end else begin
+      WCtrlData_q_2 <= WCtrlData_q_1;
+    end
+    if (reset) begin // @[MII.scala 147:31]
+      WCtrlDataStart <= 1'h0; // @[MII.scala 147:31]
+    end else if (EndBusy) begin // @[MII.scala 160:18]
+      WCtrlDataStart <= 1'h0; // @[MII.scala 161:20]
+    end else begin
+      WCtrlDataStart <= _GEN_32;
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      WCtrlDataStart_q_0 <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn) begin // @[Reg.scala 36:18]
+      WCtrlDataStart_q_0 <= WCtrlDataStart; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      WCtrlDataStart_q_1 <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn) begin // @[Reg.scala 36:18]
+      WCtrlDataStart_q_1 <= WCtrlDataStart_q_0; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      WCtrlDataStart_q0 <= 1'h0; // @[Reg.scala 35:20]
+    end else if (_WCtrlDataStart_q0_T) begin // @[Reg.scala 36:18]
+      WCtrlDataStart_q0 <= WCtrlDataStart; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[MII.scala 168:36]
+      UpdateMIIRX_DATAReg <= 1'h0; // @[MII.scala 168:36]
+    end else begin
+      UpdateMIIRX_DATAReg <= EndBusy & ~WCtrlDataStart_q0; // @[MII.scala 168:36]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      RStat_q_0 <= 1'h0; // @[Reg.scala 35:20]
+    end else begin
+      RStat_q_0 <= io_RStat;
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      RStat_q_1 <= 1'h0; // @[Reg.scala 35:20]
+    end else begin
+      RStat_q_1 <= RStat_q_0;
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      RStat_q_2 <= 1'h0; // @[Reg.scala 35:20]
+    end else begin
+      RStat_q_2 <= RStat_q_1;
+    end
+    if (reset) begin // @[MII.scala 174:27]
+      RStatStart <= 1'h0; // @[MII.scala 174:27]
+    end else if (EndBusy) begin // @[MII.scala 179:18]
+      RStatStart <= 1'h0; // @[MII.scala 180:16]
+    end else begin
+      RStatStart <= _GEN_40;
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      RStatStart_q_0 <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn) begin // @[Reg.scala 36:18]
+      RStatStart_q_0 <= RStatStart; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      RStatStart_q_1 <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn) begin // @[Reg.scala 36:18]
+      RStatStart_q_1 <= RStatStart_q_0; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      SyncStatmdcEn <= 1'h0; // @[Reg.scala 35:20]
+    end else if (mdcEn) begin // @[Reg.scala 36:18]
+      SyncStatmdcEn <= ScanStat_q_1; // @[Reg.scala 36:22]
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      ScanStat_q_0 <= 1'h0; // @[Reg.scala 35:20]
+    end else begin
+      ScanStat_q_0 <= io_ScanStat;
+    end
+    if (reset) begin // @[Reg.scala 35:20]
+      ScanStat_q_1 <= 1'h0; // @[Reg.scala 35:20]
+    end else begin
+      ScanStat_q_1 <= ScanStat_q_0;
+    end
+    if (reset) begin // @[MII.scala 203:23]
+      Nvalid <= 1'h0; // @[MII.scala 203:23]
+    end else if (_EndBusy_T_1) begin // @[MII.scala 206:46]
+      Nvalid <= 1'h0; // @[MII.scala 207:12]
+    end else begin
+      Nvalid <= _GEN_48;
+    end
+  end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+`ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  Counter = _RAND_0[7:0];
+  _RAND_1 = {1{`RANDOM}};
+  mdc = _RAND_1[0:0];
+  _RAND_2 = {1{`RANDOM}};
+  ShiftReg = _RAND_2[7:0];
+  _RAND_3 = {1{`RANDOM}};
+  Prsd = _RAND_3[15:0];
+  _RAND_4 = {1{`RANDOM}};
+  LinkFail = _RAND_4[0:0];
+  _RAND_5 = {1{`RANDOM}};
+  BitCounter = _RAND_5[6:0];
+  _RAND_6 = {1{`RANDOM}};
+  InProgress = _RAND_6[0:0];
+  _RAND_7 = {1{`RANDOM}};
+  InProgress_q_0 = _RAND_7[0:0];
+  _RAND_8 = {1{`RANDOM}};
+  InProgress_q_1 = _RAND_8[0:0];
+  _RAND_9 = {1{`RANDOM}};
+  InProgress_q_2 = _RAND_9[0:0];
+  _RAND_10 = {1{`RANDOM}};
+  EndBusy_r = _RAND_10[0:0];
+  _RAND_11 = {1{`RANDOM}};
+  EndBusy = _RAND_11[0:0];
+  _RAND_12 = {1{`RANDOM}};
+  WriteOp = _RAND_12[0:0];
+  _RAND_13 = {1{`RANDOM}};
+  LatchByte0_r = _RAND_13[0:0];
+  _RAND_14 = {1{`RANDOM}};
+  LatchByte0 = _RAND_14[0:0];
+  _RAND_15 = {1{`RANDOM}};
+  LatchByte1_r = _RAND_15[0:0];
+  _RAND_16 = {1{`RANDOM}};
+  LatchByte1 = _RAND_16[0:0];
+  _RAND_17 = {1{`RANDOM}};
+  mdoEn_r = _RAND_17[0:0];
+  _RAND_18 = {1{`RANDOM}};
+  mdoEn_r_1 = _RAND_18[0:0];
+  _RAND_19 = {1{`RANDOM}};
+  mdoEn = _RAND_19[0:0];
+  _RAND_20 = {1{`RANDOM}};
+  mdo_2d = _RAND_20[0:0];
+  _RAND_21 = {1{`RANDOM}};
+  mdo_d = _RAND_21[0:0];
+  _RAND_22 = {1{`RANDOM}};
+  mdo = _RAND_22[0:0];
+  _RAND_23 = {1{`RANDOM}};
+  WCtrlData_q_0 = _RAND_23[0:0];
+  _RAND_24 = {1{`RANDOM}};
+  WCtrlData_q_1 = _RAND_24[0:0];
+  _RAND_25 = {1{`RANDOM}};
+  WCtrlData_q_2 = _RAND_25[0:0];
+  _RAND_26 = {1{`RANDOM}};
+  WCtrlDataStart = _RAND_26[0:0];
+  _RAND_27 = {1{`RANDOM}};
+  WCtrlDataStart_q_0 = _RAND_27[0:0];
+  _RAND_28 = {1{`RANDOM}};
+  WCtrlDataStart_q_1 = _RAND_28[0:0];
+  _RAND_29 = {1{`RANDOM}};
+  WCtrlDataStart_q0 = _RAND_29[0:0];
+  _RAND_30 = {1{`RANDOM}};
+  UpdateMIIRX_DATAReg = _RAND_30[0:0];
+  _RAND_31 = {1{`RANDOM}};
+  RStat_q_0 = _RAND_31[0:0];
+  _RAND_32 = {1{`RANDOM}};
+  RStat_q_1 = _RAND_32[0:0];
+  _RAND_33 = {1{`RANDOM}};
+  RStat_q_2 = _RAND_33[0:0];
+  _RAND_34 = {1{`RANDOM}};
+  RStatStart = _RAND_34[0:0];
+  _RAND_35 = {1{`RANDOM}};
+  RStatStart_q_0 = _RAND_35[0:0];
+  _RAND_36 = {1{`RANDOM}};
+  RStatStart_q_1 = _RAND_36[0:0];
+  _RAND_37 = {1{`RANDOM}};
+  SyncStatmdcEn = _RAND_37[0:0];
+  _RAND_38 = {1{`RANDOM}};
+  ScanStat_q_0 = _RAND_38[0:0];
+  _RAND_39 = {1{`RANDOM}};
+  ScanStat_q_1 = _RAND_39[0:0];
+  _RAND_40 = {1{`RANDOM}};
+  Nvalid = _RAND_40[0:0];
+`endif // RANDOMIZE_REG_INIT
+  `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule

src/main/scala/mac/MII.scala

@@ -1,7 +1,7 @@
 package MAC
 
 import chisel3._
-import chisel3.util
+import chisel3.util._
 
 class MDIO extends Bundle{
   val mdi   = Input( Bool()) // MII Management Data In
@@ -11,208 +11,221 @@ class MDIO extends Bundle{
 }
 
 class MIIMIO extends MDIO{
-  val CtrlData = Input( UInt(16.W) )       // Control Data (to be written to the PHY reg.)
+  val Divider  = Input( UInt(8.W) )        // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
-  val Rgad = Input(UInt(5.W))              // Register Address (within the PHY)
-  val Fiad = Input( UInt(5.W) )            // PHY Address
   val NoPre = Input(Bool())                // No Preamble (no 32-bit preamble)
+
   val WCtrlData = Input(Bool())            // Write Control Data operation
+  val CtrlData = Input( UInt(16.W) )       // Control Data (to be written to the PHY reg.)
+
+  val Fiad = Input( UInt(5.W) )            // PHY Address
+  val Rgad = Input(UInt(5.W))              // Register Address (within the PHY)
+
   val RStat = Input( Bool() )              // Read Status operation
+
   val ScanStat = Input( Bool() )           // Scan Status operation
 
   val Busy = Output(Bool())                // Busy Signal
   val LinkFail = Output(Bool())            // Link Integrity Signal
   val Nvalid = Output(Bool())              // Invalid Status (qualifier for the valid scan result)
   val Prsd = Output(UInt(16.W))            // Read Status Data (data read from the PHY)
+  
   val WCtrlDataStart = Output(Bool())      // This signals resets the WCTRLDATA bit in the MIIM Command register
   val RStatStart = Output(Bool())          // This signal resets the RSTAT BIT in the MIIM Command register
   val UpdateMIIRX_DATAReg = Output(Bool()) // Updates MII RX_DATA register with read data
 
-
-
 }
 
 class MIIMBase extends Module{
   val io: MIIMIO = IO(new MIIMIO)
-}
-
-/** Connecting the Clock Generator Module */
-trait MIIMClockGen{ this: MIIMBase =>
-  val Divider = Wire( UInt(8.W) )            // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
 
 
-  val TempDivider   = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
+  val ByteSelect = Wire( Vec( 4, Bool() ) )         // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
-  val CounterPreset = ( TempDivider >> 1 ) - 1.U        // We are counting half of period
 
 
   // Counter counts half period
   val Counter  = RegInit( 1.U(8.W) )
-  val Mdc = RegInit(false.B)      // Output clock
+  val mdc = RegInit(false.B)      // Output clock
-  val CountEq0 = Counter === 0.U
+  val mdcEn    = (Counter === 0.U) & ~mdc  // Enable signal is asserted for one Clk period before mdc rises.
-  val MdcEn    = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
+  val mdcEn_n  = (Counter === 0.U) &  mdc  // Enable signal is asserted for one Clk period before mdc falls.
-  val MdcEn_n  = CountEq0 & Mdc;  // Enable signal is asserted for one Clk period before Mdc falls.
 
-  when( CountEq0 ) {
+  val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
+  val Prsd     = RegInit(0.U(16.W))
+  val LinkFail = RegInit(false.B)
+
+  
+  val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
+  val EndOp = BitCounter === 63.U     // Operation ends when the Bit Counter reaches 63    
+
+
+  val InProgress = RegInit(false.B)                                        // Operation in progress
+  val InProgress_q     = ShiftRegisters(InProgress,     3, false.B, mdcEn) // Operation in progress delayed 3 mdc cycles
+  val EndBusy =  ShiftRegister(~InProgress_q(1) & InProgress_q(2), 2, false.B, true.B)    // Generation of the EndBusy signal. It is used for ending the MII Management operation. 
+
+  val WriteOp    = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
+
+
+
+
+  io.mdc := mdc
+  io.LinkFail := LinkFail
+  io.Prsd := Prsd
+
+
+ 
+
+
+}
+
+/** Connecting the Clock Generator Module */
+trait MIIMClockGen{ this: MIIMBase =>
+
+  val TempDivider   = Mux( io.Divider < 2.U, 2.U, io.Divider ) // If smaller than 2
+  val CounterPreset = ( TempDivider >> 1 ) - 1.U               // We are counting half of period
+
+  when( Counter === 0.U ) {
+    mdc := ~mdc              // mdc is asserted every other half period
     Counter := CounterPreset
   } .otherwise{
     Counter := Counter - 1.U
   }
 
-  // Mdc is asserted every other half period
-  when(CountEq0) {
-    Mdc := ~Mdc
-  }
-
-
 }
 
 
 trait MIIMShiftReg{ this: MIIMBase =>
 
-  val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
+  val LatchByte0 = ShiftRegister(InProgress & ~WriteOp & BitCounter === "h3F".U, 2, false.B, mdcEn)   // Latch Byte selects which part of Read Status Data is updated from the shift register
-  val Prsd     = RegInit(0.U(16.W))
+  val LatchByte1 = ShiftRegister(InProgress & ~WriteOp & BitCounter === "h37".U, 2, false.B, mdcEn)   // Latch Byte selects which part of Read Status Data is updated from the shift register
-  val LinkFail = RegInit(false.B)
 
-  when(MdcEn_n){
+  ByteSelect(0) := InProgress & ((io.NoPre & (BitCounter === 0.U)) | (~io.NoPre & (BitCounter === "h20".U)));
-    when(|ByteSelect) {
+  ByteSelect(1) := InProgress & (BitCounter === "h28".U);
-      /* verilator lint_off CASEINCOMPLETE */
+  ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
+  ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
+
+  when(mdcEn_n){
+    when(ByteSelect.reduce(_|_)) {
       ShiftReg := Mux1H(Seq(
-        ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
+        ByteSelect(0) -> Cat("b01".U(2.W), ~WriteOp, WriteOp, io.Fiad(4,1)),
-        ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
+        ByteSelect(1) -> Cat(io.Fiad.extract(0), io.Rgad(4,0), "b10".U(2.W)),
-        ByteSelect === "h4".U -> CtrlData(15,8),
+        ByteSelect(2) -> io.CtrlData(15,8),
-        ByteSelect === "h8".U -> CtrlData( 7,0),
+        ByteSelect(3) -> io.CtrlData( 7,0),
       ))    
     } .otherwise{
-      ShiftReg := Cat(ShiftReg(6,0), Mdi)
+      ShiftReg := Cat(ShiftReg(6,0), io.mdi)
-      when(LatchByte.extract(0)){
+      when(LatchByte0){
-        Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
+        Prsd := Cat(Prsd(15,8), ShiftReg(6,0), io.mdi)
-        when(Rgad === 1.U){
+        when(io.Rgad === 1.U){
           LinkFail := ~ShiftReg.extract(1)  // this is bit [2], because it is not shifted yet                
         }
-      } .elsewhen(LatchByte.extract(1)){
+      } .elsewhen(LatchByte1){
-          Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
+        Prsd := Cat(ShiftReg(6,0), io.mdi, Prsd(7,0))
       }
     }
   }
 
-  val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
-
 }
 
 trait MIIMOutputCtl{ this: MIIMBase =>
 
-// Generation of the Serial Enable signal (enables the serialization of the data)
+  // Generation of the Serial Enable signal (enables the serialization of the data)
-val SerialEn =  WriteOp & InProgress &     ( BitCounter > 31.U | ( ( BitCounter === 0.U ) & NoPre ) )
+  val SerialEn =  ( WriteOp & InProgress & ( BitCounter > 31.U | ( ( BitCounter === 0.U ) & io.NoPre ) )) |
-                | ~WriteOp & InProgress & (( BitCounter > 31.U & BitCounter < 46.U ) | ( ( BitCounter === 0.U ) & NoPre ))
+                  (~WriteOp & InProgress & (( BitCounter > 31.U & BitCounter < 46.U ) | ( ( BitCounter === 0.U ) & io.NoPre )))
-
-val MdoEn  = ShiftRegisters( SerialEn | InProgress & BitCounter<32.U, 3, false.B, en = MdcEn_n)
-val Mdo_2d = RegEnable( ~SerialEn & BitCounter<32.U, false.B, MdcEn_n)
-val Mdo_d  = RegEnable( ShiftedBit | Mdo_2d,       false.B, MdcEn_n)
-val Mdo    = RegEnable( Mdo_d,                     false.B, MdcEn_n)
-
-
-
-
 
+  val mdoEn  = ShiftRegister( SerialEn | (InProgress & BitCounter<32.U), 3, false.B, mdcEn_n)
+  val mdo_2d = RegEnable( ~SerialEn & BitCounter<32.U, false.B, mdcEn_n)
+  val mdo_d  = RegEnable( ShiftReg.extract(7) | mdo_2d,       false.B, mdcEn_n)
+  val mdo    = RegEnable( mdo_d,                     false.B, mdcEn_n)
+  io.mdo := mdo
+  io.mdoEn := mdoEn
 
 }
 
 
-trait MIIM { this: MIIMBase =>
+class MIIM extends MIIMBase with MIIMClockGen with MIIMShiftReg with MIIMOutputCtl{
 
+  val WCtrlData_q = ShiftRegisters(io.WCtrlData, 3, false.B, true.B)
+  val WCtrlDataStart = RegInit(false.B)                                    // Start Write Control Data Command (positive edge detected)
+  val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, mdcEn) // Start Write Control Data Command delayed 2 mdc cycle
+  val WriteDataOp  = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1)            // Write Data Operation (positive edge detected) 
+  io.WCtrlDataStart := WCtrlDataStart
 
-  // Generation of the EndBusy signal. It is used for ending the MII Management operation.
+  // Generation of the Operation signals
-  val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
-  val EndBusy   = RegInit(false.B, EndBusy_d)
-
-
-  // Update MII RX_DATA register
-  val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
 
 
   
-
+  val StartOp = Wire(Bool()) // Start Operation (start of any of the preceding operations)
-  // Generation of the delayed signals used for positive edge triggering.
-  val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en = true.B)
-  val RStat_q     = ShiftRegisters(RStat,     3, false.B, en = true.B)
-  val ScanStat_q  = ShiftRegisters(ScanStat,  2, false.B, en = true.B)
-  val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
                         
 
 
-
-
-  // Generation of the Start Commands (Write Control Data or Read Status)
-  val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
-  val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
-  val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
-
   when( EndBusy ){
     WCtrlDataStart := false.B
+  } .elsewhen( WCtrlData_q(1) & ~WCtrlData_q(2) ){
+    WCtrlDataStart := true.B
+  }
+
+  // Update MII RX_DATA register
+  val WCtrlDataStart_q0 = RegEnable(WCtrlDataStart, false.B, ~EndBusy)
+  val UpdateMIIRX_DATAReg = RegNext(EndBusy & ~WCtrlDataStart_q0, false.B) // Updates MII RX_DATA register with read data
+  io.UpdateMIIRX_DATAReg := UpdateMIIRX_DATAReg
+
+
+
+  val RStat_q    = ShiftRegisters(io.RStat,     3, false.B, true.B)
+  val RStatStart = RegInit(false.B)                                    // Start Read Status Command (positive edge detected)
+  val RStatStart_q = ShiftRegisters(RStatStart,     2, false.B, mdcEn) // Start Read Status Command delayed 2 mdc cycles
+  val ReadStatusOp = RStatStart_q(0)     & ~RStatStart_q(1)            // Read Status Operation (positive edge detected)
+  io.RStatStart := RStatStart
+
+  when( EndBusy ){
     RStatStart := false.B
-  } .otherwise{
+  } .elsewhen(RStat_q(1) & ~RStat_q(2)){
-    when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
+    RStatStart := true.B
-      WCtrlDataStart := true.B
+  }
-    }
+
-    when(RStat_q(1) & ~RStat_q(2)){
+
-      RStatStart := true.B
+
+
+  when(mdcEn){
+    when(StartOp) {
+      InProgress := true.B
+    } .elsewhen(EndOp) {
+      InProgress := false.B
     }
   }
 
 
 
-  // Generation of the Nvalid signal (indicates when the status is invalid)
+  val ScanStat_q  = ShiftRegisters(io.ScanStat,  2, false.B, true.B)
-  val Nvalid = RegInit(false.B)
+  val SyncStatmdcEn = RegEnable(ScanStat_q(1), false.B, mdcEn) // Scan Status operation delayed at least cycles and synchronized to mdcEn
-  when( ~InProgress_q2 & InProgress_q3 ) {
+  val ScanStatusOp = SyncStatmdcEn       & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
+
+
+  val Nvalid = RegInit(false.B) // Generation of the Nvalid signal (indicates when the status is invalid)
+  io.Nvalid := Nvalid
+
+  when( ~InProgress_q(1) & InProgress_q(2) ) {
     Nvalid := false.B
-  } .elsewhen(ScanStat_q2  & ~SyncStatMdcEn) {
+  } .elsewhen(ScanStat_q(1)  & ~SyncStatmdcEn) {
     Nvalid := true.B
   }
 
 
-  // Signals used for the generation of the Operation signals (positive edge)
-
-  val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
-  val RStatStart_q     = ShiftRegisters(RStatStart,     2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
-  val InProgress_q     = ShiftRegisters(InProgress,     3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
-  val LatchByte0       = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn)   // Latch Byte selects which part of Read Status Data is updated from the shift register
-  val LatchByte1       = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn)   // Latch Byte selects which part of Read Status Data is updated from the shift register
-  val LatchByte        = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
 
 
-
+  when(mdcEn){
-  // Generation of the Operation signals
-  val WriteDataOp  = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
-  val ReadStatusOp = RStatStart_q(0)     & ~RStatStart_q(1)     // Read Status Operation (positive edge detected)
-  val ScanStatusOp = SyncStatMdcEn       & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
-  val StartOp      = WriteDataOp | ReadStatusOp | ScanStatusOp  // Start Operation (start of any of the preceding operations)
-
-  // Busy
-  val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
-
-
-  // Generation of the InProgress signal (indicates when an operation is in progress)
-  // Generation of the WriteOp signal (indicates when a write is in progress)
-  val InProgress = RegInit(false.B) // Operation in progress
-  val WriteOp    = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
-
-  when(MdcEn){
     when(StartOp) {
-      InProgress := true.B
       when( ~InProgress ){
-        WriteOp := WriteDataOp
+        WriteOp := Mux( WriteDataOp, true.B, false.B )
       }
     } .elsewhen(EndOp) {
-      InProgress := false.B
       WriteOp := false.B
     }
   }
 
-  // Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
-  val BitCounter = RegInit( 0.U(7.W) )         // Bit Counter
 
-  when( MdcEn ){
+  when( mdcEn ){
     when( InProgress ) {
-      when( NoPre &  BitCounter === 0.U ) {
+      when( io.NoPre & BitCounter === 0.U ) {
         BitCounter := "h21".U
       } .otherwise {
         BitCounter := BitCounter + 1.U
@@ -222,13 +235,10 @@ trait MIIM { this: MIIMBase =>
     }
   }
 
-  // Operation ends when the Bit Counter reaches 63        
-  val EndOp = BitCounter === 63.U // End of Operation
-  val ByteSelect = Wire( Vec( 4, Bool() ) )         // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
 
-  ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
+  StartOp := WriteDataOp | ReadStatusOp | ScanStatusOp
-  ByteSelect(1) := InProgress & (BitCounter === "h28".U);
+  io.Busy := io.WCtrlData | WCtrlDataStart | io.RStat | RStatStart | SyncStatmdcEn | EndBusy | InProgress | InProgress_q(2) | Nvalid
-  ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
-  ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
 
 }
+
+

src/test/scala/gcd/GCDSpec.scala

@@ -1,52 +0,0 @@
-// See README.md for license details.
-
-package gcd
-
-import chisel3._
-import chiseltest._
-import org.scalatest.freespec.AnyFreeSpec
-import chisel3.experimental.BundleLiterals._
-
-/**
-  * This is a trivial example of how to run this Specification
-  * From within sbt use:
-  * {{{
-  * testOnly gcd.GcdDecoupledTester
-  * }}}
-  * From a terminal shell use:
-  * {{{
-  * sbt 'testOnly gcd.GcdDecoupledTester'
-  * }}}
-  */
-class GCDSpec extends AnyFreeSpec with ChiselScalatestTester {
-
-  "Gcd should calculate proper greatest common denominator" in {
-    test(new DecoupledGcd(16)) { dut =>
-      dut.input.initSource()
-      dut.input.setSourceClock(dut.clock)
-      dut.output.initSink()
-      dut.output.setSinkClock(dut.clock)
-
-      val testValues = for { x <- 0 to 10; y <- 0 to 10} yield (x, y)
-      val inputSeq = testValues.map { case (x, y) => (new GcdInputBundle(16)).Lit(_.value1 -> x.U, _.value2 -> y.U) }
-      val resultSeq = testValues.map { case (x, y) =>
-        (new GcdOutputBundle(16)).Lit(_.value1 -> x.U, _.value2 -> y.U, _.gcd -> BigInt(x).gcd(BigInt(y)).U)
-      }
-
-      fork {
-        // push inputs into the calculator, stall for 11 cycles one third of the way
-        val (seq1, seq2) = inputSeq.splitAt(resultSeq.length / 3)
-        dut.input.enqueueSeq(seq1)
-        dut.clock.step(11)
-        dut.input.enqueueSeq(seq2)
-      }.fork {
-        // retrieve computations from the calculator, stall for 10 cycles one half of the way
-        val (seq1, seq2) = resultSeq.splitAt(resultSeq.length / 2)
-        dut.output.expectDequeueSeq(seq1)
-        dut.clock.step(10)
-        dut.output.expectDequeueSeq(seq2)
-      }.join()
-
-    }
-  }
-}

src/test/scala/gcd/test.scala

@@ -0,0 +1,13 @@
+package test
+
+import MAC._
+import chisel3._
+import chisel3.stage._
+
+object testModule extends App {
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => {
+    new MIIM()
+  })
+    ))
+}