compare test pass
This commit is contained in:
RuigeLee
@@ -1,7 +1,7 @@
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package MAC
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import chisel3._
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import chisel3.util
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import chisel3.util._
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class MDIO extends Bundle{
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val mdi = Input( Bool()) // MII Management Data In
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@@ -11,208 +11,221 @@ class MDIO extends Bundle{
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}
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class MIIMIO extends MDIO{
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val CtrlData = Input( UInt(16.W) ) // Control Data (to be written to the PHY reg.)
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val Rgad = Input(UInt(5.W)) // Register Address (within the PHY)
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val Fiad = Input( UInt(5.W) ) // PHY Address
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val Divider = Input( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
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val NoPre = Input(Bool()) // No Preamble (no 32-bit preamble)
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val WCtrlData = Input(Bool()) // Write Control Data operation
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val CtrlData = Input( UInt(16.W) ) // Control Data (to be written to the PHY reg.)
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val Fiad = Input( UInt(5.W) ) // PHY Address
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val Rgad = Input(UInt(5.W)) // Register Address (within the PHY)
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val RStat = Input( Bool() ) // Read Status operation
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val ScanStat = Input( Bool() ) // Scan Status operation
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val Busy = Output(Bool()) // Busy Signal
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val LinkFail = Output(Bool()) // Link Integrity Signal
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val Nvalid = Output(Bool()) // Invalid Status (qualifier for the valid scan result)
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val Prsd = Output(UInt(16.W)) // Read Status Data (data read from the PHY)
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val WCtrlDataStart = Output(Bool()) // This signals resets the WCTRLDATA bit in the MIIM Command register
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val RStatStart = Output(Bool()) // This signal resets the RSTAT BIT in the MIIM Command register
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val UpdateMIIRX_DATAReg = Output(Bool()) // Updates MII RX_DATA register with read data
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}
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class MIIMBase extends Module{
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val io: MIIMIO = IO(new MIIMIO)
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}
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/** Connecting the Clock Generator Module */
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trait MIIMClockGen{ this: MIIMBase =>
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val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
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val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
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val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
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val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
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// Counter counts half period
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val Counter = RegInit( 1.U(8.W) )
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val Mdc = RegInit(false.B) // Output clock
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val CountEq0 = Counter === 0.U
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val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
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val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
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val mdc = RegInit(false.B) // Output clock
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val mdcEn = (Counter === 0.U) & ~mdc // Enable signal is asserted for one Clk period before mdc rises.
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val mdcEn_n = (Counter === 0.U) & mdc // Enable signal is asserted for one Clk period before mdc falls.
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when( CountEq0 ) {
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val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
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val Prsd = RegInit(0.U(16.W))
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val LinkFail = RegInit(false.B)
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val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
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val EndOp = BitCounter === 63.U // Operation ends when the Bit Counter reaches 63
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val InProgress = RegInit(false.B) // Operation in progress
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val InProgress_q = ShiftRegisters(InProgress, 3, false.B, mdcEn) // Operation in progress delayed 3 mdc cycles
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val EndBusy = ShiftRegister(~InProgress_q(1) & InProgress_q(2), 2, false.B, true.B) // Generation of the EndBusy signal. It is used for ending the MII Management operation.
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val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
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io.mdc := mdc
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io.LinkFail := LinkFail
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io.Prsd := Prsd
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}
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/** Connecting the Clock Generator Module */
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trait MIIMClockGen{ this: MIIMBase =>
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val TempDivider = Mux( io.Divider < 2.U, 2.U, io.Divider ) // If smaller than 2
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val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
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when( Counter === 0.U ) {
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mdc := ~mdc // mdc is asserted every other half period
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Counter := CounterPreset
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} .otherwise{
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Counter := Counter - 1.U
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}
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// Mdc is asserted every other half period
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when(CountEq0) {
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Mdc := ~Mdc
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}
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}
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trait MIIMShiftReg{ this: MIIMBase =>
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val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
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val Prsd = RegInit(0.U(16.W))
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val LinkFail = RegInit(false.B)
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when(MdcEn_n){
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when(|ByteSelect) {
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/* verilator lint_off CASEINCOMPLETE */
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val LatchByte0 = ShiftRegister(InProgress & ~WriteOp & BitCounter === "h3F".U, 2, false.B, mdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
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val LatchByte1 = ShiftRegister(InProgress & ~WriteOp & BitCounter === "h37".U, 2, false.B, mdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
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ByteSelect(0) := InProgress & ((io.NoPre & (BitCounter === 0.U)) | (~io.NoPre & (BitCounter === "h20".U)));
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ByteSelect(1) := InProgress & (BitCounter === "h28".U);
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ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
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ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
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when(mdcEn_n){
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when(ByteSelect.reduce(_|_)) {
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ShiftReg := Mux1H(Seq(
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ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
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ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
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ByteSelect === "h4".U -> CtrlData(15,8),
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ByteSelect === "h8".U -> CtrlData( 7,0),
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ByteSelect(0) -> Cat("b01".U(2.W), ~WriteOp, WriteOp, io.Fiad(4,1)),
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ByteSelect(1) -> Cat(io.Fiad.extract(0), io.Rgad(4,0), "b10".U(2.W)),
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ByteSelect(2) -> io.CtrlData(15,8),
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ByteSelect(3) -> io.CtrlData( 7,0),
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))
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} .otherwise{
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ShiftReg := Cat(ShiftReg(6,0), Mdi)
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when(LatchByte.extract(0)){
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Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
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when(Rgad === 1.U){
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ShiftReg := Cat(ShiftReg(6,0), io.mdi)
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when(LatchByte0){
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Prsd := Cat(Prsd(15,8), ShiftReg(6,0), io.mdi)
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when(io.Rgad === 1.U){
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LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
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}
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} .elsewhen(LatchByte.extract(1)){
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Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
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} .elsewhen(LatchByte1){
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Prsd := Cat(ShiftReg(6,0), io.mdi, Prsd(7,0))
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}
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}
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}
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val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
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}
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trait MIIMOutputCtl{ this: MIIMBase =>
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// Generation of the Serial Enable signal (enables the serialization of the data)
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val SerialEn = WriteOp & InProgress & ( BitCounter > 31.U | ( ( BitCounter === 0.U ) & NoPre ) )
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| ~WriteOp & InProgress & (( BitCounter > 31.U & BitCounter < 46.U ) | ( ( BitCounter === 0.U ) & NoPre ))
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val MdoEn = ShiftRegisters( SerialEn | InProgress & BitCounter<32.U, 3, false.B, en = MdcEn_n)
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val Mdo_2d = RegEnable( ~SerialEn & BitCounter<32.U, false.B, MdcEn_n)
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val Mdo_d = RegEnable( ShiftedBit | Mdo_2d, false.B, MdcEn_n)
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val Mdo = RegEnable( Mdo_d, false.B, MdcEn_n)
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// Generation of the Serial Enable signal (enables the serialization of the data)
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val SerialEn = ( WriteOp & InProgress & ( BitCounter > 31.U | ( ( BitCounter === 0.U ) & io.NoPre ) )) |
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(~WriteOp & InProgress & (( BitCounter > 31.U & BitCounter < 46.U ) | ( ( BitCounter === 0.U ) & io.NoPre )))
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val mdoEn = ShiftRegister( SerialEn | (InProgress & BitCounter<32.U), 3, false.B, mdcEn_n)
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val mdo_2d = RegEnable( ~SerialEn & BitCounter<32.U, false.B, mdcEn_n)
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val mdo_d = RegEnable( ShiftReg.extract(7) | mdo_2d, false.B, mdcEn_n)
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val mdo = RegEnable( mdo_d, false.B, mdcEn_n)
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io.mdo := mdo
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io.mdoEn := mdoEn
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}
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trait MIIM { this: MIIMBase =>
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class MIIM extends MIIMBase with MIIMClockGen with MIIMShiftReg with MIIMOutputCtl{
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val WCtrlData_q = ShiftRegisters(io.WCtrlData, 3, false.B, true.B)
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val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
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val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, mdcEn) // Start Write Control Data Command delayed 2 mdc cycle
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val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
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io.WCtrlDataStart := WCtrlDataStart
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// Generation of the Operation signals
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// Generation of the EndBusy signal. It is used for ending the MII Management operation.
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val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
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val EndBusy = RegInit(false.B, EndBusy_d)
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val StartOp = Wire(Bool()) // Start Operation (start of any of the preceding operations)
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// Update MII RX_DATA register
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val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
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// Generation of the delayed signals used for positive edge triggering.
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val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en = true.B)
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val RStat_q = ShiftRegisters(RStat, 3, false.B, en = true.B)
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val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en = true.B)
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val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
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// Generation of the Start Commands (Write Control Data or Read Status)
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val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
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val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
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val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
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when( EndBusy ){
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WCtrlDataStart := false.B
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} .elsewhen( WCtrlData_q(1) & ~WCtrlData_q(2) ){
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WCtrlDataStart := true.B
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}
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// Update MII RX_DATA register
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val WCtrlDataStart_q0 = RegEnable(WCtrlDataStart, false.B, ~EndBusy)
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val UpdateMIIRX_DATAReg = RegNext(EndBusy & ~WCtrlDataStart_q0, false.B) // Updates MII RX_DATA register with read data
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io.UpdateMIIRX_DATAReg := UpdateMIIRX_DATAReg
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val RStat_q = ShiftRegisters(io.RStat, 3, false.B, true.B)
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val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
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val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, mdcEn) // Start Read Status Command delayed 2 mdc cycles
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val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
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io.RStatStart := RStatStart
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when( EndBusy ){
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RStatStart := false.B
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} .otherwise{
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when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
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WCtrlDataStart := true.B
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}
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when(RStat_q(1) & ~RStat_q(2)){
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RStatStart := true.B
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} .elsewhen(RStat_q(1) & ~RStat_q(2)){
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RStatStart := true.B
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}
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when(mdcEn){
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when(StartOp) {
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InProgress := true.B
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} .elsewhen(EndOp) {
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InProgress := false.B
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}
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}
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// Generation of the Nvalid signal (indicates when the status is invalid)
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val Nvalid = RegInit(false.B)
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when( ~InProgress_q2 & InProgress_q3 ) {
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val ScanStat_q = ShiftRegisters(io.ScanStat, 2, false.B, true.B)
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val SyncStatmdcEn = RegEnable(ScanStat_q(1), false.B, mdcEn) // Scan Status operation delayed at least cycles and synchronized to mdcEn
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val ScanStatusOp = SyncStatmdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
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val Nvalid = RegInit(false.B) // Generation of the Nvalid signal (indicates when the status is invalid)
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io.Nvalid := Nvalid
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when( ~InProgress_q(1) & InProgress_q(2) ) {
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Nvalid := false.B
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} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
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} .elsewhen(ScanStat_q(1) & ~SyncStatmdcEn) {
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Nvalid := true.B
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}
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// Signals used for the generation of the Operation signals (positive edge)
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val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
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val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
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val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
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val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
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val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
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val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
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// Generation of the Operation signals
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val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
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val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
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val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
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val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
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// Busy
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val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
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// Generation of the InProgress signal (indicates when an operation is in progress)
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// Generation of the WriteOp signal (indicates when a write is in progress)
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val InProgress = RegInit(false.B) // Operation in progress
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val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
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when(MdcEn){
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when(mdcEn){
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when(StartOp) {
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InProgress := true.B
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when( ~InProgress ){
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WriteOp := WriteDataOp
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WriteOp := Mux( WriteDataOp, true.B, false.B )
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}
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} .elsewhen(EndOp) {
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InProgress := false.B
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WriteOp := false.B
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}
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}
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// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
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val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
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when( MdcEn ){
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when( mdcEn ){
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when( InProgress ) {
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when( NoPre & BitCounter === 0.U ) {
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when( io.NoPre & BitCounter === 0.U ) {
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BitCounter := "h21".U
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} .otherwise {
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BitCounter := BitCounter + 1.U
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@@ -222,13 +235,10 @@ trait MIIM { this: MIIMBase =>
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}
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}
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// Operation ends when the Bit Counter reaches 63
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val EndOp = BitCounter === 63.U // End of Operation
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val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
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ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
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ByteSelect(1) := InProgress & (BitCounter === "h28".U);
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ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
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ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
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StartOp := WriteDataOp | ReadStatusOp | ScanStatusOp
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io.Busy := io.WCtrlData | WCtrlDataStart | io.RStat | RStatStart | SyncStatmdcEn | EndBusy | InProgress | InProgress_q(2) | Nvalid
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}
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}
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@@ -1,52 +0,0 @@
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// See README.md for license details.
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package gcd
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import chisel3._
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import chiseltest._
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import org.scalatest.freespec.AnyFreeSpec
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import chisel3.experimental.BundleLiterals._
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/**
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* This is a trivial example of how to run this Specification
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* From within sbt use:
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* {{{
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* testOnly gcd.GcdDecoupledTester
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* }}}
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* From a terminal shell use:
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* {{{
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* sbt 'testOnly gcd.GcdDecoupledTester'
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* }}}
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*/
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class GCDSpec extends AnyFreeSpec with ChiselScalatestTester {
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"Gcd should calculate proper greatest common denominator" in {
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test(new DecoupledGcd(16)) { dut =>
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dut.input.initSource()
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dut.input.setSourceClock(dut.clock)
|
||||
dut.output.initSink()
|
||||
dut.output.setSinkClock(dut.clock)
|
||||
|
||||
val testValues = for { x <- 0 to 10; y <- 0 to 10} yield (x, y)
|
||||
val inputSeq = testValues.map { case (x, y) => (new GcdInputBundle(16)).Lit(_.value1 -> x.U, _.value2 -> y.U) }
|
||||
val resultSeq = testValues.map { case (x, y) =>
|
||||
(new GcdOutputBundle(16)).Lit(_.value1 -> x.U, _.value2 -> y.U, _.gcd -> BigInt(x).gcd(BigInt(y)).U)
|
||||
}
|
||||
|
||||
fork {
|
||||
// push inputs into the calculator, stall for 11 cycles one third of the way
|
||||
val (seq1, seq2) = inputSeq.splitAt(resultSeq.length / 3)
|
||||
dut.input.enqueueSeq(seq1)
|
||||
dut.clock.step(11)
|
||||
dut.input.enqueueSeq(seq2)
|
||||
}.fork {
|
||||
// retrieve computations from the calculator, stall for 10 cycles one half of the way
|
||||
val (seq1, seq2) = resultSeq.splitAt(resultSeq.length / 2)
|
||||
dut.output.expectDequeueSeq(seq1)
|
||||
dut.clock.step(10)
|
||||
dut.output.expectDequeueSeq(seq2)
|
||||
}.join()
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
13
src/test/scala/gcd/test.scala
Normal file
13
src/test/scala/gcd/test.scala
Normal file
@@ -0,0 +1,13 @@
|
||||
package test
|
||||
|
||||
import MAC._
|
||||
import chisel3._
|
||||
import chisel3.stage._
|
||||
|
||||
object testModule extends App {
|
||||
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
|
||||
ChiselGeneratorAnnotation(() => {
|
||||
new MIIM()
|
||||
})
|
||||
))
|
||||
}
|
||||
Reference in New Issue
Block a user