From ab506a0e376867dad5ca5422b3fc943e5723fdaf Mon Sep 17 00:00:00 2001 From: bacon Date: Mon, 3 Feb 2025 07:51:54 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E6=B5=8B=E8=AF=95=E4=BB=A3?= =?UTF-8?q?=E7=A0=81=EF=BC=8C=E8=AE=A9=E6=95=B4=E4=B8=AA=E4=B8=BB=E7=AB=99?= =?UTF-8?q?=E7=9A=84=E4=BB=A3=E7=A0=81=E5=B7=A5=E4=BD=9C=E5=9C=A8RV32E?= =?UTF-8?q?=E7=9A=84=E7=BC=96=E8=AF=91=E9=80=89=E9=A1=B9=E4=B8=8B=EF=BC=8C?= =?UTF-8?q?=E4=BB=85=E4=B8=AD=E6=96=AD=E4=BB=A3=E7=A0=81=E5=B7=A5=E4=BD=9C?= =?UTF-8?q?=E5=9C=A8RV32I=E7=9A=84=E7=BC=96=E8=AF=91=E9=80=89=E9=A1=B9?= =?UTF-8?q?=E4=B8=8B=EF=BC=8C=E5=8F=AF=E4=BB=A5=E4=BC=98=E5=8C=96=E4=B8=AD?= =?UTF-8?q?=E6=96=AD=E7=9A=84=E9=80=9F=E5=BA=A6=E3=80=82=E4=BB=A3=E7=A0=81?= =?UTF-8?q?=E4=BB=85=E5=81=9A=E5=A4=87=E4=BB=BD=EF=BC=8C=E4=B8=AD=E6=96=AD?= =?UTF-8?q?=E9=83=A8=E5=88=86=E6=89=A7=E8=A1=8C=E4=B8=8D=E6=AD=A3=E5=B8=B8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Makefile | 49 +++++++++++++++++------ tb/sw/bin_2_c_array.py | 45 +++++++++++++++++++++ tb/sw/src/MstMain.c | 11 +++--- tb/sw/src/mstStartup.S | 90 ++++++++++++++++++++++++------------------ tb/sw/src/mstSvr.S | 80 +++++++++++++++++++++++++++++++++++++ 5 files changed, 219 insertions(+), 56 deletions(-) create mode 100644 tb/sw/bin_2_c_array.py create mode 100644 tb/sw/src/mstSvr.S diff --git a/Makefile b/Makefile index 8ed082a..2d01fcb 100644 --- a/Makefile +++ b/Makefile @@ -1,10 +1,13 @@ TARGET=riscv64-unknown-elf RVCC=$(TARGET)-gcc RVCCVERSION=$(shell $(RVCC) --version | grep ^$(RVCC) | sed 's/^.* //g') -MARCH=-march=rv32i -mabi=ilp32 -CFLAGS=-O2 +RV32I_MARCH=-march=rv32i -mabi=ilp32 +RV32E_MARCH=-march=rv32e -mabi=ilp32e +RV32I_CFLAGS=-O2 -D__RV32I_MARCH__ +RV32E_CFLAGS=-O2 ifeq "$(RVCCVERSION)" "12.2.0" - MARCH=-march=rv32izicsr -mabi=ilp32 + RV32I_MARCH=-march=rv32izicsr -mabi=ilp32 + RV32E_MARCH=-march=rv32ezicsr -mabi=ilp32e endif .PHONY: compile tb wave @@ -68,27 +71,49 @@ sw: rm ./tb/sw/build/* -f mkdir -p ./tb/sw/build/ - $(RVCC) -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \ + $(RVCC) -ggdb $(RV32I_MARCH) $(RV32I_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \ + -I ./tb/sw/ -I ./tb/sw/src \ + -I ./tb/sw/tl2cdr \ + -c ./tb/sw/src/mstSvr.S \ + -o ./tb/sw/build/mstSvr.o + + $(RVCC) -ggdb $(RV32I_MARCH) $(RV32I_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \ + -T ./tb/sw/linker.lds \ + ./tb/sw/build/mstSvr.o \ + -o ./tb/sw/build/mstSvr.elf + + $(TARGET)-objcopy -O binary ./tb/sw/build/mstSvr.elf ./tb/sw/build/mstSvr.bin + + python3 ./tb/sw/bin_2_c_array.py ./tb/sw/build/mstSvr.bin ./tb/sw/src/mstSvr.c + + $(RVCC) -ggdb $(RV32E_MARCH) $(RV32E_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ + -I ./tb/sw/ -I ./tb/sw/src \ + -I ./tb/sw/tl2cdr \ + -c ./tb/sw/src/mstSvr.c \ + -o ./tb/sw/build/mstSvr.o + + $(RVCC) -ggdb $(RV32E_MARCH) $(RV32E_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \ -I ./tb/sw/ -I ./tb/sw/src \ -I ./tb/sw/tl2cdr \ -c ./tb/sw/src/mstStartup.S \ -o ./tb/sw/build/mstStartup.o - $(RVCC) -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ + $(RVCC) -ggdb $(RV32E_MARCH) $(RV32E_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ -I ./tb/sw/ -I ./tb/sw/src \ -I ./tb/sw/tl2cdr \ -c ./tb/sw/src/MstMain.c \ -o ./tb/sw/build/mstMain.o - # $(RVCC) -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \ + # $(RVCC) -ggdb $(RV32E_MARCH) $(RV32E_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \ # -I ./tb/sw/ -I ./tb/sw/src \ # -c ./tb/sw/src/mstMain.S \ # -o ./tb/sw/build/mstMain.o - $(RVCC) -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \ + $(RVCC) -ggdb $(RV32E_MARCH) $(RV32E_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \ -T ./tb/sw/linker.lds \ ./tb/sw/build/mstStartup.o \ ./tb/sw/build/mstMain.o \ + ./tb/sw/build/mstSvr.o \ -o ./tb/sw/build/mstTest.elf $(TARGET)-objcopy -O binary ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.bin @@ -98,25 +123,23 @@ sw: $(TARGET)-objcopy -O verilog ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.verilog sed -i 's/@400/@000/g' ./tb/sw/build/mstTest.verilog - - - $(RVCC) -O3 -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ + $(RVCC) -O3 -ggdb $(RV32I_MARCH) $(RV32I_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ -I ./tb/sw/ -I ./tb/sw/src \ -I ./tb/sw/tl2cdr \ -c ./tb/sw/src/SlvMain.c \ -o ./tb/sw/build/slvMain.o - $(RVCC) -Os -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \ + $(RVCC) -Os -ggdb $(RV32I_MARCH) $(RV32I_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \ -I ./tb/sw/ -I ./tb/sw/src \ -c ./tb/sw/src/slvStartup.S \ -o ./tb/sw/build/slvStartup.o - # $(RVCC) -Os -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \ + # $(RVCC) -Os -ggdb $(RV32I_MARCH) $(RV32I_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \ # -I ./tb/sw/ -I ./tb/sw/src \ # -c ./tb/sw/src/slvMain.S \ # -o ./tb/sw/build/slvMain.o - $(RVCC) -Os -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \ + $(RVCC) -Os -ggdb $(RV32I_MARCH) $(RV32I_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \ -T ./tb/sw/linker.lds \ ./tb/sw/build/slvStartup.o \ ./tb/sw/build/slvMain.o \ diff --git a/tb/sw/bin_2_c_array.py b/tb/sw/bin_2_c_array.py new file mode 100644 index 0000000..16c8b52 --- /dev/null +++ b/tb/sw/bin_2_c_array.py @@ -0,0 +1,45 @@ +#!/usr/bin/python3 + +def bin_2_c_array_file(bin_file, c_file): + # 打开二进制文件和输出的 C 文件 + with open(bin_file, 'rb') as bf, open(c_file, 'w') as cf: + # 写入文件头 + cf.write('#include "stdint.h"\n') + #cf.write('const uint8_t mst_svr_code[] __attribute__((aligned(32), section(".trap_entry"))) = {\n') + cf.write('const uint8_t mst_svr_code[] __attribute__((aligned(32))) = {\n') + + all_data = bf.read() + + # 将二进制内容按每4字节分割并转换为十六进制字符串 + for i in range(len(all_data)): + cf.write('0x%02x, ' % all_data[i]) + if ((i + 1) % 16) == 0: + cf.write('\n') + if ((len(all_data) + 1) % 16) != 0: + cf.write('\n};\n') + else: + cf.write('};\n') + + ''' + wstr = '' + for i in range(len(all_data)): + wstr = wstr + '0x%02x, ' % all_data[i] + if ((i + 1) % 16) == 0: + cf.write(wstr + '\n') + wstr = '' + if len(wstr) != 0: + cf.write(wstr) + cf.write('\n};\n') + ''' + cf.close() + bf.close() + + +if __name__ == '__main__': + import sys + #import os + #print(len(sys.argv), sys.argv, os.getcwd()) + # 运行脚本 + #bin_to_coe_file("./tb/sw/build/slvTest.bin", "./tb/sw/build/slvTest.coe") + if len(sys.argv) >= 3: + bin_2_c_array_file(sys.argv[1], sys.argv[2]) \ No newline at end of file diff --git a/tb/sw/src/MstMain.c b/tb/sw/src/MstMain.c index d4e4b56..a847fcd 100644 --- a/tb/sw/src/MstMain.c +++ b/tb/sw/src/MstMain.c @@ -56,9 +56,6 @@ void plic_handle(){ return; } - - - static inline void error() { while(1); } @@ -72,7 +69,8 @@ static inline void error() { // extern volatile uint32_t *cdr_rxLen = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read // extern volatile uint32_t *cdr_rxFifo = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read - +//extern const uint8_t mst_svr_code[]; +//uint32_t (*init_svr_code)(void); void main() { @@ -88,6 +86,8 @@ void main() uint32_t led = 0; + //init_svr_code = (uint32_t (*)(void))mst_svr_code; + *plic_enable_0_31 = 1 << CDR_INT_TXEND | 1 << CDR_INT_RXERROR | 1 << CDR_INT_RXSTART | 1 << CDR_INT_RXEND; *plic_priority_TxEnd = 1; *plic_priority_RxError = 1; @@ -104,6 +104,8 @@ void main() *plic_threshold_0 = 0; } + //while (init_svr_code() != 1); + *cdr_softReset = 1; //复位脉冲 @@ -130,7 +132,6 @@ void main() // led = 1; // } - //发送下行包头 *cdr_txLen = 520; //总长520 *cdr_txFifo = (512 << 20) |( 0 << 16) | 0x0000; //负载长度512，操作数0， 参数全0 diff --git a/tb/sw/src/mstStartup.S b/tb/sw/src/mstStartup.S index ad45596..1a12508 100644 --- a/tb/sw/src/mstStartup.S +++ b/tb/sw/src/mstStartup.S @@ -2,6 +2,13 @@ .extern main .extern plic_handle +.extern mst_svr_code +.extern plic_claim +.extern flag_intTxEnd +.extern flag_intRxError +.extern flag_intRxStart +.extern flag_intRxEnd + .globl _prog_start .section .text.init @@ -22,6 +29,7 @@ _prog_start: li x13, 0 li x14, 0 li x15, 0 +#ifdef __RV32I_MARCH__ li x16, 0 li x17, 0 li x18, 0 @@ -38,15 +46,39 @@ _prog_start: li x29, 0 li x30, 0 li x31, 0 +#endif + + li sp, 0x40011000 + + lui t0, %hi(plic_claim) + lw a0, %lo(plic_claim)(t0) + #la a0, plic_claim + + lui t0, %hi(flag_intTxEnd) + lw a1, %lo(flag_intTxEnd)(t0) + #la a1, flag_intTxEnd + + lui t0, %hi(flag_intRxError) + lw a2, %lo(flag_intRxError)(t0) + #la a2, flag_intRxError + + lui t0, %hi(flag_intRxStart) + lw a3, %lo(flag_intRxStart)(t0) + #la a3, flag_intRxStart + + lui t0, %hi(flag_intRxEnd) + lw a4, %lo(flag_intRxEnd)(t0) + #la a4, flag_intRxEnd + + call mst_svr_code + mv t0, a0 #la t0, trap_entry - la t0, opt_trap_entry + #la t0, opt_trap_entry csrw mtvec, t0 li t0, 1 << 11 csrw mie, t0 - li sp, 0x40011000 - csrr t0, mstatus ori t0, t0, 1<<3 csrw mstatus, t0 @@ -56,7 +88,6 @@ _prog_start: ecall - .balign 32 .section .trap_entry, "ax", %progbits trap_entry: @@ -77,6 +108,7 @@ trap_entry: sw a3,52(sp) sw a4,56(sp) sw a5,60(sp) +#ifdef __RV32I_MARCH__ sw a6,64(sp) sw a7,68(sp) sw s2,72(sp) @@ -93,6 +125,7 @@ trap_entry: sw t4,116(sp) sw t5,120(sp) sw t6,124(sp) +#endif csrr t0, mstatus # 读取 mstatus 寄存器 andi t0, t0, ~(1 << 3) # 清除 MIE 位 (全局中断禁用) @@ -119,6 +152,7 @@ trap_entry: lw a3,52(sp) lw a4,56(sp) lw a5,60(sp) +#ifdef __RV32I_MARCH__ lw a6,64(sp) lw a7,68(sp) lw s2,72(sp) @@ -135,10 +169,9 @@ trap_entry: lw t4,116(sp) lw t5,120(sp) lw t6,124(sp) +#endif addi sp,sp,136 - - mret #.macro define_const name, value @@ -147,13 +180,6 @@ trap_entry: ## 使用宏定义常量 #define_const CDR_INT_TXEND, 14 - -.extern plic_claim -.extern flag_intTxEnd -.extern flag_intRxError -.extern flag_intRxStart -.extern flag_intRxEnd - opt_trap_entry: addi sp,sp,-136 @@ -196,58 +222,47 @@ opt_trap_entry: andi t0, t0, ~(1 << 3) # 清除 MIE 位 (全局中断禁用) csrw mstatus, t0 # 写回 mstatus 寄存器 -# t0 = &plic_claim lui t1, %hi(plic_claim) - lw t0, %lo(plic_claim)(t1) - -# t1 = *plic_claim - lw t1, 0(t0) + lw t0, %lo(plic_claim)(t1) # t0 = &plic_claim + + lw t1, 0(t0) # t1 = *plic_claim + sw t1, 0(t0) # *plic_claim = t1 + li s0, CDR_INT_TXEND -#_if (t1 != s0) goto 1f - bne t1, s0, 1f + bne t1, s0, 1f #_if (t1 != s0) goto 1f -#_else - lui s0,%hi(flag_intTxEnd) + lui s0,%hi(flag_intTxEnd) #_else li s1,1 sw s1,%lo(flag_intTxEnd)(s0) j 4f 1: li s0, CDR_INT_RXERROR -#_if (t1 != s0) goto 2f - bne t1, s0, 2f + bne t1, s0, 2f #_if (t1 != s0) goto 2f -#_else - lui s0,%hi(flag_intRxError) + lui s0,%hi(flag_intRxError) #_else li s1,1 sw s1,%lo(flag_intRxError)(s0) j 4f 2: li s0, CDR_INT_RXSTART -#_if (t1 != s0) goto 3f - bne t1, s0, 3f + bne t1, s0, 3f #_if (t1 != s0) goto 3f -#_else - lui s0,%hi(flag_intRxStart) + lui s0,%hi(flag_intRxStart) #_else li s1,1 sw s1,%lo(flag_intRxStart)(s0) j 4f 3: li s0, CDR_INT_RXEND + bne t1, s0, 4f #_if (t1 != s0) goto 4f -#_if (t1 != s0) goto 4f - beq t1, s0, 4f - -#_else - lui s0,%hi(flag_intRxEnd) + lui s0,%hi(flag_intRxEnd) #_else li s1,1 sw s1,%lo(flag_intRxEnd)(s0) 4: - sw t1, 0(t0) - csrr t0, mstatus ori t0, t0, 1<<3 csrw mstatus, t0 @@ -292,4 +307,3 @@ opt_trap_entry: - diff --git a/tb/sw/src/mstSvr.S b/tb/sw/src/mstSvr.S new file mode 100644 index 0000000..8f95443 --- /dev/null +++ b/tb/sw/src/mstSvr.S @@ -0,0 +1,80 @@ +#include "tl2cdr.h" + +.globl _prog_start +.globl _rv32i_plic_handle + +.section .text.init, "ax", %progbits + +#if 0 +#其他代码全部使用RV32E编译，仅此代码采用 RV32I 编译，故而可以使用x0, x16~x31寄存器 +#为了方便，不再使用ABI中的别名，直接使用x0, x16~x31；x1~x15使用ABI中定义的别名 +#endif + +_prog_start: + li x16, 0 + + mv x17, a0 # plic_claim + mv x18, a1 # flag_intTxEnd + mv x19, a2 # flag_intRxError + mv x20, a3 # flag_intRxStart + mv x21, a4 # flag_intRxEnd + mv x22, x0 + + #lui x23, %hi(_rv32i_plic_handle) + #lw x24, %lo(_rv32i_plic_handle)(x23) + + la x24, _rv32i_plic_handle + + li x25, 1 + li x26, 0 + li x27, 0 + li x28, CDR_INT_TXEND + li x29, CDR_INT_RXERROR + li x30, CDR_INT_RXSTART + li x31, CDR_INT_RXSTART + + + mv a0, x24 + + li x23, 0 + li x24, 0 + ret + + .balign 32 +_rv32i_plic_handle: + csrr x16, mstatus # 读取 mstatus 寄存器 + andi x16, x16, ~(1 << 3) # 清除 MIE 位 (全局中断禁用) + csrw mstatus, x16 # 写回 mstatus 寄存器 + + lw x23, 0(x17) # x23 = *plic_claim + sw x23, 0(x17) # *plic_claim = x23 + + #li x25, 1 + + li x24, CDR_INT_TXEND + bne x23, x24, 1f #_if (x23 != x24) goto 1f + sw x25, 0(x18) #_else + j 4f + +1: + li x24, CDR_INT_RXERROR + bne x23, x24, 2f #_if (x23 != x24) goto 2f + sw x25, 0(x19) #_else + j 4f + +2: + li x24, CDR_INT_RXSTART + bne x23, x24, 3f #_if (x23 != x24) goto 3f + sw x25, 0(x20) #_else + j 4f + +3: + li x24, CDR_INT_RXEND + bne x23, x24, 4f #_if (x23 != x24) goto 4f + sw x25, 0(x21) #_else + +4: + csrr x16, mstatus + ori x16, x16, 1<<3 + csrw mstatus, x16 + mret