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物理层和链路层各自有header，需要打包两次

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RuigeLee
2024-10-17 11:43:16 +08:00
parent 84b978cbc9
commit ab0fab00fa
2 changed files with 22 additions and 21 deletions
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41
src/main/scala/backBoard/shin/ShinSlv.scala
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@@ -49,13 +49,13 @@ abstract class ShinSlvPhyBase extends Module{
require( headByte == 8 ) require( headByte == 8 )
require( headByte > 4, "At Least 4 more additional cycles to ensure CRC Failure boardcast to next nodes!\n") require( headByte > 4, "At Least 4 more additional cycles to ensure CRC Failure boardcast to next nodes!\n")
val OpInitByte = 1 val OpInitByte = 8
val OpBoardCastByte = 16 val OpBoardCastByte = 16
val OpUniCastByte = 32 val OpUniCastByte = 32
val maxLocalByte = OpInitByte max OpBoardCastByte max OpUniCastByte val maxLocalByte = OpInitByte max OpBoardCastByte max OpUniCastByte
val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + 4 ) ) val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), 8 + headByte + 4 ) )
val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) ) //4 is reserve val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) ) //4 is reserve
val isLastDevice = Wire(Bool()) val isLastDevice = Wire(Bool())
@@ -74,7 +74,8 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
val downOldHead = Reg( new Header_Info_Bundle ) val downOldHead = Reg( new Header_Info_Bundle )
val downNewHead = Reg( new Header_Info_Bundle ) val downNewHead = Reg( new Header_Info_Bundle )
val downPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) )
downStreamCdrIn.io.axis <> downPendBuf.io.enq
val downRecvStateNext = Wire( UInt(3.W) ) val downRecvStateNext = Wire( UInt(3.W) )
val downRecvStateCurr = RegNext( downRecvStateNext, 0.U ) val downRecvStateCurr = RegNext( downRecvStateNext, 0.U )
@@ -95,23 +96,23 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
val isLastDevice: Bool val isLastDevice: Bool
downRecvStateNext := Mux1H(Seq( downRecvStateNext := Mux1H(Seq(
(downRecvStateCurr === DownRecvStateIdle ) -> Mux( downStreamCdrIn.io.axis.valid, DownRecvStateOHead, DownRecvStateIdle ), (downRecvStateCurr === DownRecvStateIdle ) -> Mux( downPendBuf.io.deq.valid, DownRecvStateOHead, DownRecvStateIdle ),
(downRecvStateCurr === DownRecvStateOHead) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === ((headByte)-1).U, DownRecvStateSData, DownRecvStateOHead), DownRecvStateIdle ), DownRecvStateOHead), (downRecvStateCurr === DownRecvStateOHead) -> Mux( downPendBuf.io.deq.fire, Mux( ~downPendBuf.io.deq.bits.tlast, Mux(downRecvCnt === ((headByte)-1).U, DownRecvStateSData, DownRecvStateOHead), DownRecvStateIdle ), DownRecvStateOHead),
(downRecvStateCurr === DownRecvStateSData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (downLocalDataByte -1.U), Mux( downRecvCnt === (downOldHead.length - 1.U), DownRecvStateCRC, DownRecvStateFData ), DownRecvStateSData), DownRecvStateIdle ), DownRecvStateSData), (downRecvStateCurr === DownRecvStateSData) -> Mux( downPendBuf.io.deq.fire, Mux( ~downPendBuf.io.deq.bits.tlast, Mux(downRecvCnt === (downLocalDataByte -1.U), Mux( downRecvCnt === (downOldHead.length - 1.U), DownRecvStateCRC, DownRecvStateFData ), DownRecvStateSData), DownRecvStateIdle ), DownRecvStateSData),
(downRecvStateCurr === DownRecvStateFData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (downForwardDataByte -1.U) , DownRecvStateCRC, DownRecvStateFData), DownRecvStateIdle ), DownRecvStateFData), (downRecvStateCurr === DownRecvStateFData) -> Mux( downPendBuf.io.deq.fire, Mux( ~downPendBuf.io.deq.bits.tlast, Mux(downRecvCnt === (downForwardDataByte -1.U) , DownRecvStateCRC, DownRecvStateFData), DownRecvStateIdle ), DownRecvStateFData),
(downRecvStateCurr === DownRecvStateCRC ) -> Mux( downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast, DownRecvStateIdle, DownRecvStateCRC ), (downRecvStateCurr === DownRecvStateCRC ) -> Mux( downPendBuf.io.deq.fire & downPendBuf.io.deq.bits.tlast, DownRecvStateIdle, DownRecvStateCRC ),
)) ))
when( downRecvStateCurr =/= downRecvStateNext ){ when( downRecvStateCurr =/= downRecvStateNext ){
downRecvCnt := 0.U downRecvCnt := 0.U
} .elsewhen( downStreamCdrIn.io.axis.fire ){ } .elsewhen( downPendBuf.io.deq.fire ){
downRecvCnt := downRecvCnt + 1.U downRecvCnt := downRecvCnt + 1.U
} }
//--------------- //---------------
when( downRecvStateCurr === DownRecvStateOHead & downStreamCdrIn.io.axis.fire ){ when( downRecvStateCurr === DownRecvStateOHead & downPendBuf.io.deq.fire ){
downOldHead := Cat( downOldHead.asUInt.tail(8), downStreamCdrIn.io.axis.bits.tdata ).asTypeOf(new Header_Info_Bundle) downOldHead := Cat( downOldHead.asUInt.tail(8), downPendBuf.io.deq.bits.tdata ).asTypeOf(new Header_Info_Bundle)
} }
@@ -124,18 +125,18 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
} }
when( downRecvStateCurr === DownRecvStateSData & downStreamCdrIn.io.axis.fire ){ when( downRecvStateCurr === DownRecvStateSData & downPendBuf.io.deq.fire ){
downRegTemp(downRecvCnt) := downStreamCdrIn.io.axis.bits.tdata downRegTemp(downRecvCnt) := downPendBuf.io.deq.bits.tdata
} }
//--------------- //---------------
downStreamFifo.io.enq.valid := downStreamFifo.io.enq.valid :=
downRecvStateCurr === DownRecvStateFData & downStreamCdrIn.io.axis.fire & ~isLastDevice downRecvStateCurr === DownRecvStateFData & downPendBuf.io.deq.fire & ~isLastDevice
downStreamFifo.io.enq.bits.tdata := downStreamCdrIn.io.axis.bits.tdata downStreamFifo.io.enq.bits.tdata := downPendBuf.io.deq.bits.tdata
downStreamFifo.io.enq.bits.tuser := downStreamCdrIn.io.axis.bits.tuser downStreamFifo.io.enq.bits.tuser := downPendBuf.io.deq.bits.tuser
downStreamFifo.io.enq.bits.tlast := downRecvCnt === (downForwardDataByte -1.U) | downStreamCdrIn.io.axis.bits.tlast downStreamFifo.io.enq.bits.tlast := downRecvCnt === (downForwardDataByte -1.U) | downPendBuf.io.deq.bits.tlast
downStreamCdrIn.io.axis.ready := downPendBuf.io.deq.ready :=
(downRecvStateCurr === DownRecvStateOHead) | (downRecvStateCurr === DownRecvStateOHead) |
(downRecvStateCurr === DownRecvStateSData) | (downRecvStateCurr === DownRecvStateSData) |
((downRecvStateCurr === DownRecvStateFData) & downStreamFifo.io.enq.ready) | ((downRecvStateCurr === DownRecvStateFData) & downStreamFifo.io.enq.ready) |
@@ -155,7 +156,7 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
} .elsewhen( downRecvStateCurr === DownRecvStateFData & downRecvStateNext === DownRecvStateIdle ){ } .elsewhen( downRecvStateCurr === DownRecvStateFData & downRecvStateNext === DownRecvStateIdle ){
isDownStreamError := true.B isDownStreamError := true.B
printf("Warning, Wrong Package Received in DownStream, That could not happened!\n") printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
} .elsewhen( downRecvStateCurr === DownRecvStateCRC & (downRecvCnt > 3.U | (downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast & downRecvCnt < 3.U)) ){ } .elsewhen( downRecvStateCurr === DownRecvStateCRC & (downRecvCnt > 3.U | (downPendBuf.io.deq.fire & downPendBuf.io.deq.bits.tlast & downRecvCnt < 3.U)) ){
isDownStreamError := true.B isDownStreamError := true.B
printf("Warning, Wrong Package Received in DownStream, That could not happened!\n") printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
} .elsewhen( isDownNewHeadCreated & downOldHead.length < downLocalDataByte ){ //本包的负载不能满足本级数据需求，传输错误 } .elsewhen( isDownNewHeadCreated & downOldHead.length < downLocalDataByte ){ //本包的负载不能满足本级数据需求，传输错误
@@ -443,7 +444,7 @@ trait ShinSlvLinkInit{ this: ShinSlvLinkBase =>
val isInit = RegInit(false.B) val isInit = RegInit(false.B)
val isLastInit = Reg(Bool()) val isLastInit = RegInit(false.B)
val slvID = Reg(UInt(7.W)) val slvID = Reg(UInt(7.W))
val slvNum = Reg(UInt(7.W)) val slvNum = Reg(UInt(7.W))
val slvRTC = Reg(UInt(64.W)) val slvRTC = Reg(UInt(64.W))

2
tb/ShinBack_tb.v
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@@ -230,7 +230,7 @@ end
initial begin initial begin
# 100000 # 10000000
$finish; $finish;
end end