diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 165d241..0626e48 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -84,6 +84,10 @@ class CommonRegisterBundle extends Bundle{ val syncPeroid = UInt(32.W) val recoTimeStamp = UInt(64.W) //时钟补偿寄存器 + val localPeroid = UInt(32.W) + val localPoint = UInt(64.W) + + val custom = Vec( 128, UInt(8.W) ) val smUsedDepth = Vec(8, UInt(8.W)) @@ -416,6 +420,21 @@ abstract class InterfaceBase extends Module{ (addr === "h145".U ) -> cReg.syncOffset(3)(15,8), (addr === "h146".U ) -> cReg.syncOffset(3)(23,16), (addr === "h147".U ) -> cReg.syncOffset(3)(31,24), + + (addr === "h148".U ) -> cReg.localPoint(7,0), + (addr === "h149".U ) -> cReg.localPoint(15,8), + (addr === "h14a".U ) -> cReg.localPoint(23,16), + (addr === "h14b".U ) -> cReg.localPoint(31,24), + (addr === "h14c".U ) -> cReg.localPoint(39,32), + (addr === "h14d".U ) -> cReg.localPoint(47,40), + (addr === "h14e".U ) -> cReg.localPoint(55,48), + (addr === "h14f".U ) -> cReg.localPoint(63,56), + + (addr === "h150".U ) -> cReg.localPeroid(7,0), + (addr === "h151".U ) -> cReg.localPeroid(15,8), + (addr === "h152".U ) -> cReg.localPeroid(23,16), + (addr === "h153".U ) -> cReg.localPeroid(31,24), + ) ++ ( 0 until 128 ).map{ i => ( addr === ("h180".U(16.W) + i.U ) ) -> cReg.custom(i) @@ -721,13 +740,15 @@ trait InterfaceSync{ this: InterfaceBase => val syncPoint = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint val syncPeroid = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid + val localPoint = RegInit(0.U(64.W)); cReg.localPoint := localPoint + val localPeroid = RegInit(0.U(32.W)); cReg.localPeroid := localPeroid val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0 for( i <- 0 until 4 ) { cReg.syncOffset(i) := syncOffset(i) } - when( isEnW & isSlvMode ){ + when( isEnW ){ when( addrw === "h120".U ){ syncCfg := dataw } @@ -768,6 +789,36 @@ trait InterfaceSync{ this: InterfaceBase => syncPeroid := Cat( dataw, syncPeroid(23,0) ) } + .elsewhen( addrw === "h148".U ){ + localPoint := Cat( localPoint(63,8), dataw ) + } .elsewhen( addrw === "h149".U ){ + localPoint := Cat( localPoint(63,16), dataw, localPoint(7,0) ) + } .elsewhen( addrw === "h14a".U ){ + localPoint := Cat( localPoint(63,24), dataw, localPoint(15,0) ) + } .elsewhen( addrw === "h14b".U ){ + localPoint := Cat( localPoint(63,32), dataw, localPoint(23,0) ) + } .elsewhen( addrw === "h14c".U ){ + localPoint := Cat( localPoint(63,40), dataw, localPoint(31,0) ) + } .elsewhen( addrw === "h14d".U ){ + localPoint := Cat( localPoint(63,48), dataw, localPoint(39,0) ) + } .elsewhen( addrw === "h14e".U ){ + localPoint := Cat( localPoint(63,56), dataw, localPoint(47,0) ) + } .elsewhen( addrw === "h14f".U ){ + localPoint := Cat( dataw, localPoint(55,0) ) + } + + .elsewhen( addrw === "h150".U ){ + localPeroid := Cat( localPeroid(31,8), dataw ) + } .elsewhen( addrw === "h151".U ){ + localPeroid := Cat( localPeroid(31,16), dataw, localPeroid(7,0) ) + } .elsewhen( addrw === "h152".U ){ + localPeroid := Cat( localPeroid(31,24), dataw, localPeroid(15,0) ) + } .elsewhen( addrw === "h153".U ){ + localPeroid := Cat( dataw, localPeroid(23,0) ) + } + + + for( i <- 1 until 4 ){ when( addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){ syncOffset(i) := Cat( syncOffset(i)(31,8), dataw ) @@ -783,7 +834,7 @@ trait InterfaceSync{ this: InterfaceBase => - when( io.lvds.isEnW & isSlvMode ){ + when( io.lvds.isEnW ){ when( io.lvds.addrw === "h120".U ){ syncCfg := io.lvds.dataw @@ -825,6 +876,35 @@ trait InterfaceSync{ this: InterfaceBase => syncPeroid := Cat( io.lvds.dataw, syncPeroid(23,0) ) } + .elsewhen( io.lvds.addrw === "h148".U ){ + localPoint := Cat( localPoint(63,8), io.lvds.dataw ) + } .elsewhen( io.lvds.addrw === "h149".U ){ + localPoint := Cat( localPoint(63,16), io.lvds.dataw, localPoint(7,0) ) + } .elsewhen( io.lvds.addrw === "h14a".U ){ + localPoint := Cat( localPoint(63,24), io.lvds.dataw, localPoint(15,0) ) + } .elsewhen( io.lvds.addrw === "h14b".U ){ + localPoint := Cat( localPoint(63,32), io.lvds.dataw, localPoint(23,0) ) + } .elsewhen( io.lvds.addrw === "h14c".U ){ + localPoint := Cat( localPoint(63,40), io.lvds.dataw, localPoint(31,0) ) + } .elsewhen( io.lvds.addrw === "h14d".U ){ + localPoint := Cat( localPoint(63,48), io.lvds.dataw, localPoint(39,0) ) + } .elsewhen( io.lvds.addrw === "h14e".U ){ + localPoint := Cat( localPoint(63,56), io.lvds.dataw, localPoint(47,0) ) + } .elsewhen( io.lvds.addrw === "h14f".U ){ + localPoint := Cat( io.lvds.dataw, localPoint(55,0) ) + } + + .elsewhen( io.lvds.addrw === "h150".U ){ + localPeroid := Cat( localPeroid(31,8), io.lvds.dataw ) + } .elsewhen( io.lvds.addrw === "h151".U ){ + localPeroid := Cat( localPeroid(31,16), io.lvds.dataw, localPeroid(7,0) ) + } .elsewhen( io.lvds.addrw === "h152".U ){ + localPeroid := Cat( localPeroid(31,24), io.lvds.dataw, localPeroid(15,0) ) + } .elsewhen( io.lvds.addrw === "h153".U ){ + localPeroid := Cat( io.lvds.dataw, localPeroid(23,0) ) + } + + for( i <- 1 until 4 ){ when( io.lvds.addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){ syncOffset(i) := Cat( syncOffset(i)(31,8), io.lvds.dataw ) @@ -898,6 +978,14 @@ trait InterfaceSync{ this: InterfaceBase => io.sync(2) := cReg.syncCfg.extract(2) & syncSign(2) io.sync(3) := cReg.syncCfg.extract(3) & syncSign(3) + + val isLocalSyncInt = cReg.localPoint === cReg.recoTimeStamp + + when( isLocalSyncInt ){ //时间到达localSync时间点 + localPoint := cReg.localPoint + cReg.localPeroid + } + + } trait InterfaceWdt{ this: InterfaceBase => @@ -992,7 +1080,19 @@ trait InterfaceSystem{ this: InterfaceBase => } //主站发送周期到了 + val isLocalSyncInt: Bool + when( isLocalSyncInt ){ + intStatus(2) := true.B + } + //外部latch中断 + val isLatchEvent = + (RegNext( cReg.event.latchStatus(0) ) =/= cReg.event.latchStatus(0)) | + (RegNext( cReg.event.latchStatus(1) ) =/= cReg.event.latchStatus(1)) + + when(isLatchEvent){ + intStatus(3) := true.B + } //看门狗溢出 val isWdtTrigAndEnable = (0 until 18).map{ i => (io.wdtTrigger(i) & cReg.wdtEnable(i))}.reduce(_|_) @@ -1052,7 +1152,8 @@ trait InterfaceSystem{ this: InterfaceBase => val trigIntPulse = (io.intMstTrig(0) & cReg.intEnable(0)) | //主站发送完成 (io.intMstTrig(1) & cReg.intEnable(1)) | //主站接收完成 - false.B | //主站发送周期到了 + (isLocalSyncInt & cReg.intEnable(2)) | //主站发送周期到了 + (isLatchEvent & cReg.intEnable(3)) | //latch Event (~RegNext(isWdtTrigAndEnable, false.B) & isWdtTrigAndEnable & cReg.intEnable(4)) | //主站接收看门狗溢出 (0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求 (0 until 4).map{ i => io.intTransEnd(i) & cReg.intEnable(16+i)}.reduce(_|_) | //传输完成请求 16,17,18,19 @@ -1078,8 +1179,8 @@ trait InterfaceSystem{ this: InterfaceBase => trait InterfaceEvent{ this: InterfaceBase => - val isPosedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(2), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) )) - val isNegedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(3), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) )) + val isPosedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(2), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) )) + val isNegedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(3), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) )) val isPosedgeLatch = for( i <- 0 until 2 ) yield RegInit(false.B) val isNegedgeLatch = for( i <- 0 until 2 ) yield RegInit(false.B)