从机上下行机制分叉

This commit is contained in:
RuigeLee
2024-06-28 15:20:22 +08:00
parent 862028dac7
commit a9f4fd18ab
5 changed files with 8 additions and 5 deletions

View File

@@ -32,6 +32,8 @@ abstract class BackBoardSlvBase extends Module{
val downRegTemp = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
val isCrcPass = io.lvdsSlv.downstream_rx_crc_valid & ~io.lvdsSlv.downstream_rx_crc_err
}
@@ -48,7 +50,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
downCnt := 0.U
}
val isCrcPass = io.lvdsSlv.downstream_rx_crc_valid & ~io.lvdsSlv.downstream_rx_crc_err
// when( io.lvdsSlv.downstream_rx_crc_valid ){
// when( ~io.lvdsSlv.downstream_rx_crc_err ){

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@@ -112,7 +112,7 @@ trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>
class DIn16 extends BackBoardSlvLocal
class DIn16 extends BackBoardSlvLocal with BackBoardSlvDown with BackBoardSlvUp
with BackBoardSlvStatusPR
with BackBoardSlvIn16{

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@@ -19,7 +19,7 @@ trait BackBoardSlvOut16{ this: BackBoardSlvLocal =>
}
class DOut16 extends BackBoardSlvLocal
class DOut16 extends BackBoardSlvLocal with BackBoardSlvDown with BackBoardSlvUp
with BackBoardSlvStatusPR
with BackBoardSlvOut16{
val out = IO(Output(UInt(16.W)))

View File

@@ -12,7 +12,7 @@ class ManualParamBundle extends Bundle{
}
abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown with BackBoardSlvUp{
abstract class BackBoardSlvLocal extends BackBoardSlvBase{
val param = IO(Input( new ManualParamBundle ))

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@@ -96,7 +96,8 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
}
class Qei extends BackBoardSlvLocal with BackBoardSlvStatusPR with BackBoardSlvQei{
class Qei extends BackBoardSlvLocal with BackBoardSlvDown with BackBoardSlvUp
with BackBoardSlvStatusPR with BackBoardSlvQei{
val phaseAIO = for( i <- 0 until 2 ) yield { IO(Input(Bool())) }
val phaseBIO = for( i <- 0 until 2 ) yield { IO(Input(Bool())) }
val phaseZIO = for( i <- 0 until 2 ) yield { IO(Input(Bool())) }