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增加子报文尾，放置workcnt

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This commit is contained in:
Ruige Lee
2025-06-24 10:23:46 +08:00
parent a4594f77de
commit a7f27f5bf0
3 changed files with 372 additions and 280 deletions
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87
src/main/scala/backBoard/shin/SlaveSendGen.scala
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@@ -15,7 +15,8 @@ class SlaveSendGenIO extends Bundle{
val frameReq = Flipped(Decoupled( new FrameHeader ))
val subMsgReq = Flipped(Decoupled( new SubMsgTxInfo ))
val subMsgHeadReq = Flipped(Decoupled( new SubMsgTxInfo ))
val subMsgTailReq = Flipped(Decoupled( new SubMsgTail ))
val send = Decoupled(new AXIS_Bundle(8))
@@ -39,8 +40,8 @@ class SlaveSendGen extends Module{
val STATE_FRAME_HEADER = 1.U //长度/ /保留2bits //包类型
val STATE_SUBMSG_HEADER = 2.U
val STATE_SUBMSG_DATA = 3.U
val STATE_CRC = 4.U //CRC校验
//val STATE_ERROR = 5.U
val STATE_SUBMSG_TAIL = 4.U
val STATE_CRC = 5.U //CRC校验
val STATE_WAIT = 6.U
@@ -64,22 +65,22 @@ class SlaveSendGen extends Module{
val frameInfo = Reg(new FrameHeader)
val subMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) }
val subMsgHeadInfo = Reg(new SubMsgTxInfo)
val subMsgTailInfo = Reg(new SubMsgTail)
val isPingFill = RegInit(false.B)
val isPingEmit = RegInit(false.B)
when( io.frameReq.fire ){
frameInfo := io.frameReq.bits
}
when( io.subMsgReq.fire ){
when( isPingFill ){
subMsgInfo(0) := io.subMsgReq.bits
} .otherwise{
subMsgInfo(1) := io.subMsgReq.bits
}
when( io.subMsgHeadReq.fire ){
subMsgHeadInfo := io.subMsgHeadReq.bits
}
when( io.subMsgTailReq.fire ){
subMsgTailInfo := io.subMsgTailReq.bits
}
@@ -90,7 +91,7 @@ class SlaveSendGen extends Module{
when( io.send.fire ){
when( stateCurr === STATE_FRAME_HEADER ){
frameLenCnt := 0.U
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER || stateCurr === STATE_SUBMSG_DATA ){
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER || stateCurr === STATE_SUBMSG_DATA || stateCurr === STATE_SUBMSG_TAIL ){
frameLenCnt := frameLenCnt + 1.U
}
}
@@ -104,36 +105,38 @@ class SlaveSendGen extends Module{
val subMsgInfoSel = Mux( isPingEmit, subMsgInfo(0), subMsgInfo(1) )
io.frameReq.ready := true.B
io.subMsgReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER
io.subMsgHeadReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER
io.subMsgTailReq.ready := stateCurr =/= STATE_SUBMSG_TAIL & stateNext === STATE_SUBMSG_TAIL
stateNext := Mux1H(Seq(
(stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ),
(stateCurr === STATE_FRAME_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, Mux(
frameInfo.frameStyle === FRAME_STYLE_COMMON,
Mux(io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
Mux(io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
STATE_CRC ),
STATE_FRAME_HEADER), STATE_FRAME_HEADER ),
(stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (8-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER),
(stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (6-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER),
(stateCurr === STATE_SUBMSG_DATA) -> Mux( io.send.fire,
Mux( lengthCnt === subMsgInfoSel.length-1.U, //已经发送完成该子报文
Mux( lengthCnt === subMsgHeadInfo.length-1.U, STATE_SUBMSG_TAIL, STATE_SUBMSG_DATA ), //已经发送完成该子报文
STATE_SUBMSG_DATA ),
(stateCurr === STATE_SUBMSG_TAIL) -> Mux( io.send.fire,
Mux( lengthCnt === (2-1).U, //已经发送完成该子报文尾
Mux( frameLenCnt === frameInfo.frameLenAim -1.U, STATE_CRC, //主报文长度达到， 进CRC
Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT ) ), //主报文长度未到，进下一个子报文
STATE_SUBMSG_DATA
), STATE_SUBMSG_DATA ),
Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT ) ), //主报文长度未到，进下一个子报文
STATE_SUBMSG_TAIL
), STATE_SUBMSG_TAIL ),
(stateCurr === STATE_CRC) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC),
// (stateCurr === STATE_ERROR) -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR),
(stateCurr === STATE_WAIT) -> Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
(stateCurr === STATE_WAIT) -> Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
))
io.data(0).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgInfoSel.source === 0.U)
io.data(1).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgInfoSel.source === 1.U)
io.data(0).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 0.U)
io.data(1).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 1.U)
assert( ~(io.data(0).ready & ~io.data(0).valid) )
assert( ~(io.data(1).ready & ~io.data(1).valid) )
@@ -143,7 +146,8 @@ class SlaveSendGen extends Module{
io.send.valid :=
(stateCurr === STATE_FRAME_HEADER) |
(stateCurr === STATE_SUBMSG_HEADER) |
(stateCurr === STATE_SUBMSG_DATA & ( (io.data(0).valid & subMsgInfoSel.source === 0.U) | (io.data(1).valid & subMsgInfoSel.source === 1.U) )) |
(stateCurr === STATE_SUBMSG_DATA & ( (io.data(0).valid & subMsgHeadInfo.source === 0.U) | (io.data(1).valid & subMsgHeadInfo.source === 1.U) )) |
(stateCurr === STATE_SUBMSG_TAIL) |
(stateCurr === STATE_CRC)
@@ -155,25 +159,29 @@ class SlaveSendGen extends Module{
))
val tdata_submsg_header = Mux1H(Seq(
(lengthCnt === 0.U) -> subMsgInfoSel.devIndex(13,6),
(lengthCnt === 1.U) -> Cat( subMsgInfoSel.devIndex(5,0), subMsgInfoSel.style),
(lengthCnt === 2.U) -> subMsgInfoSel.address(15,8),
(lengthCnt === 3.U) -> subMsgInfoSel.address(7,0),
(lengthCnt === 4.U) -> Cat(subMsgInfoSel.operator, subMsgInfoSel.length(11,8)),
(lengthCnt === 5.U) -> subMsgInfoSel.length(7,0),
(lengthCnt === 6.U) -> subMsgInfoSel.workCnt(15,8),
(lengthCnt === 7.U) -> subMsgInfoSel.workCnt(7,0),
(lengthCnt === 0.U) -> subMsgHeadInfo.devIndex(13,6),
(lengthCnt === 1.U) -> Cat( subMsgHeadInfo.devIndex(5,0), subMsgHeadInfo.style),
(lengthCnt === 2.U) -> subMsgHeadInfo.address(15,8),
(lengthCnt === 3.U) -> subMsgHeadInfo.address(7,0),
(lengthCnt === 4.U) -> Cat(subMsgHeadInfo.operator, subMsgHeadInfo.length(11,8)),
(lengthCnt === 5.U) -> subMsgHeadInfo.length(7,0),
))
val tdata_submsg_data = Mux1H(Seq(
(subMsgInfoSel.source === 0.U) -> io.data(0).bits,
(subMsgInfoSel.source === 1.U) -> io.data(1).bits,
(subMsgHeadInfo.source === 0.U) -> io.data(0).bits,
(subMsgHeadInfo.source === 1.U) -> io.data(1).bits,
))
val tdata_submsg_tail = Mux1H(Seq(
(lengthCnt === 0.U) -> subMsgTailInfo.workCnt(15,8),
(lengthCnt === 1.U) -> subMsgTailInfo.workCnt( 7,0),
))
crc.io.dataIn := Mux1H(Seq(
(stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header,
(stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header,
(stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data,
(stateCurr === STATE_SUBMSG_TAIL) -> tdata_submsg_tail,
))
@@ -188,6 +196,7 @@ class SlaveSendGen extends Module{
(stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header,
(stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header,
(stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data,
(stateCurr === STATE_SUBMSG_TAIL) -> tdata_submsg_tail,
(stateCurr === STATE_CRC) -> tdata_crc,
))