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删除物间相关模拟寄存器

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This commit is contained in:
RuigeLee
2026-01-15 14:24:24 +08:00
parent e8f1d5b1f1
commit a78b8edd1a
2 changed files with 0 additions and 71 deletions
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47
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -44,15 +44,6 @@ class CommonRegisterBundle extends Bundle{
val uniCode = UInt(64.W)
val pllCtrl = UInt(32.W)
val xtal = UInt(16.W)
val anamuxSel = UInt(5.W)
val ldo2p5 = UInt(8.W)
val ldo1p1 = UInt(8.W)
val refTop = UInt(3.W)
val bias = UInt(2.W)
val div4 = UInt(4.W)
val dwupEx = Bool()
val b8b4Sel = Bool()
val cdrParam = UInt(8.W)
@@ -214,7 +205,6 @@ class InterfaceIO extends Bundle{
val hwSerial = Input(UInt(48.W))
val uniCode = Input(UInt(64.W))
val isPllCfg = Output(Bool())
}
@@ -281,26 +271,11 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
(addr === "h43".U ) -> cReg.softResetCode(3),
) ++
((0 until 4).map{ i =>
(addr === ("h44".U(16.W) + i.U) ) -> cReg.pllCtrl( 8*i+7,8*i+0 )
}) ++
((0 until 2).map{ i =>
(addr === ("h48".U(16.W) + i.U) ) -> cReg.xtal( 8*i+7,8*i+0 )
}) ++
Seq(
(addr === "h4a".U ) -> cReg.dwupEx,
(addr === "h4c".U ) -> cReg.b8b4Sel,
(addr === "h4e".U ) -> cReg.cdrParam,
(addr === "h50".U ) -> cReg.anamuxSel,
(addr === "h51".U ) -> cReg.ldo2p5,
(addr === "h52".U ) -> cReg.ldo1p1,
(addr === "h53".U ) -> cReg.refTop,
(addr === "h54".U ) -> cReg.bias,
(addr === "h55".U ) -> cReg.div4,
(addr === "h70".U ) -> cReg.intEnable(7,0),
(addr === "h71".U ) -> cReg.intEnable(15,8),
(addr === "h72".U ) -> cReg.intEnable(23,16),
@@ -1280,29 +1255,7 @@ trait InterfaceEvent{ this: InterfaceBase =>
}
trait InterfaceAnalog{ this: InterfaceBase =>
cReg.pllCtrl :=
Cat(
RegEnable( dataw, "h80".U(8.W), isEnW & addrw === "h47".U ),
RegEnable( dataw, "h00".U(8.W), isEnW & addrw === "h46".U ),
RegEnable( dataw, "h31".U(8.W), isEnW & addrw === "h45".U ),
RegEnable( dataw, "h3c".U(8.W), isEnW & addrw === "h44".U )
)
cReg.xtal :=
Cat(
RegEnable( dataw, "h05".U(8.W), isEnW & addrw === "h49".U ),
RegEnable( dataw, "h15".U(8.W), isEnW & addrw === "h48".U )
)
cReg.anamuxSel := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h50".U )
cReg.ldo2p5 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h51".U )
cReg.ldo1p1 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h52".U )
cReg.refTop := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h53".U )
cReg.bias := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h54".U )
cReg.div4 := RegEnable( dataw(3,0), "h1".U(4.W), isEnW & addrw === "h55".U )
io.isPllCfg := isEnW & addrw === "h45".U
}
trait InterfaceStat{ this: InterfaceBase =>

24
src/main/scala/backBoard/shin/MstSlvSwitch.scala
View File

@@ -24,17 +24,6 @@ class TopBase_IO_Bundle extends Bundle{
val hwSerial = Input(UInt(48.W))
val uniCode = Input(UInt(64.W))
val pllCtrl = Output(UInt(32.W))
val xtal = Output(UInt(12.W))
val anamuxSel = Output(UInt(5.W))
val ldo2p5 = Output(UInt(8.W))
val ldo1p1 = Output(UInt(8.W))
val refTop = Output(UInt(3.W))
val bias = Output(UInt(2.W))
val div4 = Output(UInt(4.W))
val spiSel = Output(UInt(2.W))
val isPllCfg = Output(Bool())
}
@@ -103,19 +92,6 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
io.iSync := interface.io.sync
io.pllCtrl := interface.io.cReg.pllCtrl
io.xtal := interface.io.cReg.xtal
io.anamuxSel := interface.io.cReg.anamuxSel
io.ldo2p5 := interface.io.cReg.ldo2p5
io.ldo1p1 := interface.io.cReg.ldo1p1
io.refTop := interface.io.cReg.refTop
io.bias := interface.io.cReg.bias
io.div4 := interface.io.cReg.div4
io.spiSel := interface.io.cReg.spiSel
io.isPllCfg := interface.io.isPllCfg
val sram = Seq(
for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },