代码堆完，开始编译
This commit is contained in:
RuigeLee
@@ -29,18 +29,19 @@
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// `define DEBUGASM
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// `define DEBUG
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`ifdef DEBUG
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`define debug(debug_command) debug_command
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`else
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`ifndef PICORV32_REGS
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`define PICORV32_REGS picosoc_regs
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`endif
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`define debug(debug_command)
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`endif
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`ifdef DEBUGNETS
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`define FORMAL_KEEP (* keep *)
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`else
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`define FORMAL_KEEP
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`endif
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`define assert(assert_expr) empty_statement
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@@ -808,17 +809,6 @@ module picorv32 #(
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end
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`endif
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`ifdef DEBUG
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always @(posedge clk) begin
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if (dbg_next) begin
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if (&dbg_insn_opcode[1:0])
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$display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
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else
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$display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
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end
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end
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`endif
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always @(posedge clk) begin
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is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
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is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
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@@ -2270,454 +2260,21 @@ module picorv32_pcpi_div (
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end
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endmodule
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/***************************************************************
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* picorv32_axi
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***************************************************************/
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module picorv32_axi #(
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parameter [ 0:0] ENABLE_COUNTERS = 1,
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parameter [ 0:0] ENABLE_COUNTERS64 = 1,
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parameter [ 0:0] ENABLE_REGS_16_31 = 1,
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] TWO_STAGE_SHIFT = 1,
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parameter [ 0:0] BARREL_SHIFTER = 0,
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parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
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parameter [ 0:0] TWO_CYCLE_ALU = 0,
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parameter [ 0:0] COMPRESSED_ISA = 0,
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parameter [ 0:0] CATCH_MISALIGN = 1,
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parameter [ 0:0] CATCH_ILLINSN = 1,
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parameter [ 0:0] ENABLE_PCPI = 0,
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parameter [ 0:0] ENABLE_MUL = 0,
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parameter [ 0:0] ENABLE_FAST_MUL = 0,
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parameter [ 0:0] ENABLE_DIV = 0,
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parameter [ 0:0] ENABLE_IRQ = 0,
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parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
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parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
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parameter [ 0:0] ENABLE_TRACE = 0,
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parameter [ 0:0] REGS_INIT_ZERO = 0,
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parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
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parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
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parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
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parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
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parameter [31:0] STACKADDR = 32'h ffff_ffff
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) (
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input clk, resetn,
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output trap,
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// AXI4-lite master memory interface
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output mem_axi_awvalid,
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input mem_axi_awready,
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output [31:0] mem_axi_awaddr,
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output [ 2:0] mem_axi_awprot,
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output mem_axi_wvalid,
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input mem_axi_wready,
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output [31:0] mem_axi_wdata,
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output [ 3:0] mem_axi_wstrb,
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input mem_axi_bvalid,
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output mem_axi_bready,
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output mem_axi_arvalid,
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input mem_axi_arready,
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output [31:0] mem_axi_araddr,
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output [ 2:0] mem_axi_arprot,
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input mem_axi_rvalid,
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output mem_axi_rready,
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input [31:0] mem_axi_rdata,
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// Pico Co-Processor Interface (PCPI)
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output pcpi_valid,
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output [31:0] pcpi_insn,
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output [31:0] pcpi_rs1,
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output [31:0] pcpi_rs2,
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input pcpi_wr,
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input [31:0] pcpi_rd,
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input pcpi_wait,
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input pcpi_ready,
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// IRQ interface
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input [31:0] irq,
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output [31:0] eoi,
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// Trace Interface
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output trace_valid,
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output [35:0] trace_data
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module picosoc_regs (
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input clk, wen,
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input [5:0] waddr,
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input [5:0] raddr1,
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input [5:0] raddr2,
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input [31:0] wdata,
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output [31:0] rdata1,
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output [31:0] rdata2
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);
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wire mem_valid;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [ 3:0] mem_wstrb;
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wire mem_instr;
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wire mem_ready;
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wire [31:0] mem_rdata;
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reg [31:0] regs [0:31];
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picorv32_axi_adapter axi_adapter (
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.clk (clk ),
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.resetn (resetn ),
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.mem_axi_awvalid(mem_axi_awvalid),
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.mem_axi_awready(mem_axi_awready),
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.mem_axi_awaddr (mem_axi_awaddr ),
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.mem_axi_awprot (mem_axi_awprot ),
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.mem_axi_wvalid (mem_axi_wvalid ),
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.mem_axi_wready (mem_axi_wready ),
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.mem_axi_wdata (mem_axi_wdata ),
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.mem_axi_wstrb (mem_axi_wstrb ),
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.mem_axi_bvalid (mem_axi_bvalid ),
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.mem_axi_bready (mem_axi_bready ),
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.mem_axi_arvalid(mem_axi_arvalid),
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.mem_axi_arready(mem_axi_arready),
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.mem_axi_araddr (mem_axi_araddr ),
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.mem_axi_arprot (mem_axi_arprot ),
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.mem_axi_rvalid (mem_axi_rvalid ),
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.mem_axi_rready (mem_axi_rready ),
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.mem_axi_rdata (mem_axi_rdata ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata )
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);
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always @(posedge clk)
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if (wen) regs[waddr[4:0]] <= wdata;
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picorv32 #(
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.ENABLE_COUNTERS (ENABLE_COUNTERS ),
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.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
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.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
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.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
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.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
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.BARREL_SHIFTER (BARREL_SHIFTER ),
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.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
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.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
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.COMPRESSED_ISA (COMPRESSED_ISA ),
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.CATCH_MISALIGN (CATCH_MISALIGN ),
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.CATCH_ILLINSN (CATCH_ILLINSN ),
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.ENABLE_PCPI (ENABLE_PCPI ),
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.ENABLE_MUL (ENABLE_MUL ),
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.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
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.ENABLE_DIV (ENABLE_DIV ),
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.ENABLE_IRQ (ENABLE_IRQ ),
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.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
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.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
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.ENABLE_TRACE (ENABLE_TRACE ),
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.REGS_INIT_ZERO (REGS_INIT_ZERO ),
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.MASKED_IRQ (MASKED_IRQ ),
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.LATCHED_IRQ (LATCHED_IRQ ),
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.PROGADDR_RESET (PROGADDR_RESET ),
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.PROGADDR_IRQ (PROGADDR_IRQ ),
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.STACKADDR (STACKADDR )
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) picorv32_core (
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.clk (clk ),
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.resetn (resetn),
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.trap (trap ),
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.mem_valid(mem_valid),
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.mem_addr (mem_addr ),
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.mem_wdata(mem_wdata),
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.mem_wstrb(mem_wstrb),
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.mem_instr(mem_instr),
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.mem_ready(mem_ready),
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.mem_rdata(mem_rdata),
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.pcpi_valid(pcpi_valid),
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.pcpi_insn (pcpi_insn ),
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.pcpi_rs1 (pcpi_rs1 ),
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.pcpi_rs2 (pcpi_rs2 ),
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.pcpi_wr (pcpi_wr ),
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.pcpi_rd (pcpi_rd ),
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.pcpi_wait (pcpi_wait ),
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.pcpi_ready(pcpi_ready),
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.irq(irq),
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.eoi(eoi),
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.trace_valid(trace_valid),
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.trace_data (trace_data)
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);
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assign rdata1 = regs[raddr1[4:0]];
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assign rdata2 = regs[raddr2[4:0]];
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endmodule
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/***************************************************************
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* picorv32_axi_adapter
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***************************************************************/
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module picorv32_axi_adapter (
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input clk, resetn,
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// AXI4-lite master memory interface
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output mem_axi_awvalid,
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input mem_axi_awready,
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output [31:0] mem_axi_awaddr,
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output [ 2:0] mem_axi_awprot,
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output mem_axi_wvalid,
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input mem_axi_wready,
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output [31:0] mem_axi_wdata,
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output [ 3:0] mem_axi_wstrb,
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input mem_axi_bvalid,
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output mem_axi_bready,
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output mem_axi_arvalid,
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input mem_axi_arready,
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output [31:0] mem_axi_araddr,
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output [ 2:0] mem_axi_arprot,
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input mem_axi_rvalid,
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output mem_axi_rready,
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input [31:0] mem_axi_rdata,
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// Native PicoRV32 memory interface
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input mem_valid,
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input mem_instr,
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output mem_ready,
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input [31:0] mem_addr,
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input [31:0] mem_wdata,
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input [ 3:0] mem_wstrb,
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output [31:0] mem_rdata
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);
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reg ack_awvalid;
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reg ack_arvalid;
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reg ack_wvalid;
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reg xfer_done;
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assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
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assign mem_axi_awaddr = mem_addr;
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assign mem_axi_awprot = 0;
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assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid;
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assign mem_axi_araddr = mem_addr;
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assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;
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assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid;
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assign mem_axi_wdata = mem_wdata;
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assign mem_axi_wstrb = mem_wstrb;
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assign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
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assign mem_axi_bready = mem_valid && |mem_wstrb;
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assign mem_axi_rready = mem_valid && !mem_wstrb;
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assign mem_rdata = mem_axi_rdata;
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always @(posedge clk) begin
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if (!resetn) begin
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ack_awvalid <= 0;
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end else begin
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xfer_done <= mem_valid && mem_ready;
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if (mem_axi_awready && mem_axi_awvalid)
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ack_awvalid <= 1;
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if (mem_axi_arready && mem_axi_arvalid)
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ack_arvalid <= 1;
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if (mem_axi_wready && mem_axi_wvalid)
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ack_wvalid <= 1;
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if (xfer_done || !mem_valid) begin
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ack_awvalid <= 0;
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ack_arvalid <= 0;
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ack_wvalid <= 0;
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end
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end
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end
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endmodule
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/***************************************************************
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* picorv32_wb
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***************************************************************/
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module picorv32_wb #(
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parameter [ 0:0] ENABLE_COUNTERS = 1,
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parameter [ 0:0] ENABLE_COUNTERS64 = 1,
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parameter [ 0:0] ENABLE_REGS_16_31 = 1,
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] TWO_STAGE_SHIFT = 1,
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parameter [ 0:0] BARREL_SHIFTER = 0,
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parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
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parameter [ 0:0] TWO_CYCLE_ALU = 0,
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parameter [ 0:0] COMPRESSED_ISA = 0,
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parameter [ 0:0] CATCH_MISALIGN = 1,
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parameter [ 0:0] CATCH_ILLINSN = 1,
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parameter [ 0:0] ENABLE_PCPI = 0,
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parameter [ 0:0] ENABLE_MUL = 0,
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parameter [ 0:0] ENABLE_FAST_MUL = 0,
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parameter [ 0:0] ENABLE_DIV = 0,
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parameter [ 0:0] ENABLE_IRQ = 0,
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parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
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parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
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parameter [ 0:0] ENABLE_TRACE = 0,
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parameter [ 0:0] REGS_INIT_ZERO = 0,
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parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
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parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
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parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
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parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
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parameter [31:0] STACKADDR = 32'h ffff_ffff
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) (
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output trap,
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// Wishbone interfaces
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input wb_rst_i,
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input wb_clk_i,
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output reg [31:0] wbm_adr_o,
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output reg [31:0] wbm_dat_o,
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input [31:0] wbm_dat_i,
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output reg wbm_we_o,
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output reg [3:0] wbm_sel_o,
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output reg wbm_stb_o,
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input wbm_ack_i,
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output reg wbm_cyc_o,
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// Pico Co-Processor Interface (PCPI)
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output pcpi_valid,
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output [31:0] pcpi_insn,
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output [31:0] pcpi_rs1,
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output [31:0] pcpi_rs2,
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input pcpi_wr,
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input [31:0] pcpi_rd,
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input pcpi_wait,
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input pcpi_ready,
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// IRQ interface
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input [31:0] irq,
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output [31:0] eoi,
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// Trace Interface
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output trace_valid,
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output [35:0] trace_data,
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output mem_instr
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);
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wire mem_valid;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [ 3:0] mem_wstrb;
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reg mem_ready;
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reg [31:0] mem_rdata;
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wire clk;
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wire resetn;
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assign clk = wb_clk_i;
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assign resetn = ~wb_rst_i;
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picorv32 #(
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.ENABLE_COUNTERS (ENABLE_COUNTERS ),
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.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
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.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
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.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
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.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
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.BARREL_SHIFTER (BARREL_SHIFTER ),
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.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
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.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
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.COMPRESSED_ISA (COMPRESSED_ISA ),
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.CATCH_MISALIGN (CATCH_MISALIGN ),
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.CATCH_ILLINSN (CATCH_ILLINSN ),
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.ENABLE_PCPI (ENABLE_PCPI ),
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.ENABLE_MUL (ENABLE_MUL ),
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.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
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.ENABLE_DIV (ENABLE_DIV ),
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.ENABLE_IRQ (ENABLE_IRQ ),
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.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
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.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
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.ENABLE_TRACE (ENABLE_TRACE ),
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.REGS_INIT_ZERO (REGS_INIT_ZERO ),
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.MASKED_IRQ (MASKED_IRQ ),
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.LATCHED_IRQ (LATCHED_IRQ ),
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.PROGADDR_RESET (PROGADDR_RESET ),
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.PROGADDR_IRQ (PROGADDR_IRQ ),
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.STACKADDR (STACKADDR )
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) picorv32_core (
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.clk (clk ),
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.resetn (resetn),
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.trap (trap ),
|
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.mem_valid(mem_valid),
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.mem_addr (mem_addr ),
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.mem_wdata(mem_wdata),
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.mem_wstrb(mem_wstrb),
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.mem_instr(mem_instr),
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.mem_ready(mem_ready),
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.mem_rdata(mem_rdata),
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.pcpi_valid(pcpi_valid),
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.pcpi_insn (pcpi_insn ),
|
||||
.pcpi_rs1 (pcpi_rs1 ),
|
||||
.pcpi_rs2 (pcpi_rs2 ),
|
||||
.pcpi_wr (pcpi_wr ),
|
||||
.pcpi_rd (pcpi_rd ),
|
||||
.pcpi_wait (pcpi_wait ),
|
||||
.pcpi_ready(pcpi_ready),
|
||||
|
||||
.irq(irq),
|
||||
.eoi(eoi),
|
||||
|
||||
|
||||
.trace_valid(trace_valid),
|
||||
.trace_data (trace_data)
|
||||
);
|
||||
|
||||
localparam IDLE = 2'b00;
|
||||
localparam WBSTART = 2'b01;
|
||||
localparam WBEND = 2'b10;
|
||||
|
||||
reg [1:0] state;
|
||||
|
||||
wire we;
|
||||
assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
|
||||
|
||||
always @(posedge wb_clk_i) begin
|
||||
if (wb_rst_i) begin
|
||||
wbm_adr_o <= 0;
|
||||
wbm_dat_o <= 0;
|
||||
wbm_we_o <= 0;
|
||||
wbm_sel_o <= 0;
|
||||
wbm_stb_o <= 0;
|
||||
wbm_cyc_o <= 0;
|
||||
state <= IDLE;
|
||||
end else begin
|
||||
case (state)
|
||||
IDLE: begin
|
||||
if (mem_valid) begin
|
||||
wbm_adr_o <= mem_addr;
|
||||
wbm_dat_o <= mem_wdata;
|
||||
wbm_we_o <= we;
|
||||
wbm_sel_o <= mem_wstrb;
|
||||
|
||||
wbm_stb_o <= 1'b1;
|
||||
wbm_cyc_o <= 1'b1;
|
||||
state <= WBSTART;
|
||||
end else begin
|
||||
mem_ready <= 1'b0;
|
||||
|
||||
wbm_stb_o <= 1'b0;
|
||||
wbm_cyc_o <= 1'b0;
|
||||
wbm_we_o <= 1'b0;
|
||||
end
|
||||
end
|
||||
WBSTART:begin
|
||||
if (wbm_ack_i) begin
|
||||
mem_rdata <= wbm_dat_i;
|
||||
mem_ready <= 1'b1;
|
||||
|
||||
state <= WBEND;
|
||||
|
||||
wbm_stb_o <= 1'b0;
|
||||
wbm_cyc_o <= 1'b0;
|
||||
wbm_we_o <= 1'b0;
|
||||
end
|
||||
end
|
||||
WBEND: begin
|
||||
mem_ready <= 1'b0;
|
||||
|
||||
state <= IDLE;
|
||||
end
|
||||
default:
|
||||
state <= IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
@@ -1,139 +0,0 @@
|
||||
package BACK
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
import org.chipsalliance.cde.config._
|
||||
|
||||
abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
|
||||
abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
|
||||
|
||||
case object BackParamsKey extends Field[BackSetting]
|
||||
|
||||
|
||||
|
||||
|
||||
case class BackSetting(
|
||||
){
|
||||
|
||||
}
|
||||
|
||||
trait HasBackParameters {
|
||||
implicit val p: Parameters
|
||||
|
||||
val backSetting = p(BackParamsKey)
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
class BackSubSys( )(implicit p: Parameters) extends LazyModule with HasBackParameters {
|
||||
|
||||
class AXI4MasterNode(portParams: Seq[AXI4MasterPortParameters])
|
||||
val AXI4SlaveNode(portParams: Seq[AXI4SlavePortParameters])
|
||||
|
||||
|
||||
|
||||
val cdrNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
|
||||
managers = Seq(TLSlaveParameters.v1(
|
||||
address = Seq(AddressSet(0x40000000L, 0xffL)),
|
||||
regionType = RegionType.UNCACHED,
|
||||
executable = true,
|
||||
supportsGet = TransferSizes(32/8, 32/8),
|
||||
supportsPutFull = TransferSizes(32/8, 32/8),
|
||||
supportsPutPartial = TransferSizes(32/8, 32/8)
|
||||
)),
|
||||
beatBytes = 32/8)))
|
||||
|
||||
val sram = LazyModule(new AXI4RAM(
|
||||
address = Seq(AddressSet(0x80000000L, 0xffffL)),
|
||||
cacheable = false,
|
||||
executable = true,
|
||||
beatBytes = 4,
|
||||
devName = Some("SRAM"),
|
||||
wcorrupt = false))
|
||||
|
||||
|
||||
val uart = LazyModule( new UART(
|
||||
busWidthBytes = 4,
|
||||
c = UARTParams(
|
||||
address = BigInt(0x50000000L),
|
||||
initBaudRate = BigInt(115200),
|
||||
)) )
|
||||
|
||||
val gpio = LazyModule(new GPIO(busWidthBytes = 4, c = GPIOParams(
|
||||
address = BigInt(0x60000000L),
|
||||
width = 16,
|
||||
)))
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
lazy val module: BackSubSysImp = new BackSubSysImp(this)
|
||||
}
|
||||
|
||||
class BackSubSysImp(outer: BackSubSys) extends LazyModuleImp(outer) with HasBackParameters {
|
||||
class BackSubSysIO extends Bundle{
|
||||
val overCLK = Input(Bool())
|
||||
val uDatIn = Input(Bool())
|
||||
val uDatOut = Output(Bool())
|
||||
val dDatIn = Input(Bool())
|
||||
val dDatOut = Output(Bool())
|
||||
}
|
||||
|
||||
|
||||
val ( bus, edge ) = chipLinkMasterNode.in.head
|
||||
|
||||
|
||||
val io: BackSubSysIO = IO(new BackSubSysIO)
|
||||
|
||||
val cdr = for( i <- 0 until 2 ) yield { Module(new TLCDR(edge)) }
|
||||
|
||||
cdr(0).io.overCLK := io.overCLK
|
||||
cdr(1).io.overCLK := io.overCLK
|
||||
|
||||
cdr(0).io.datIn := io.uDatIn
|
||||
io.uDatOut := cdr(0).io.uDatOut
|
||||
cdr(1).io.datIn := io.dDatIn
|
||||
io.dDatOut := cdr(1).io.uDatOut
|
||||
|
||||
|
||||
cdr(0).io.tla.valid := bus.a.valid & bus.a.address(7) === "h0".U
|
||||
cdr(1).io.tla.valid := bus.a.valid & bus.a.address(7) === "h1".U
|
||||
cdr(0).io.tla.bits := bus.a.bits
|
||||
bus.a.ready :=
|
||||
(bus.a.address(7) === "h0".U & cdr(0).io.tla.ready) |
|
||||
(bus.a.address(7) === "h1".U & cdr(1).io.tla.ready)
|
||||
|
||||
bus.d.valid := cdr(0).io.tld.valid | cdr(1).io.tld.valid
|
||||
bus.d.bits := Mux1H(Seq(
|
||||
cdr(0).io.tld.valid -> cdr(0).io.tld.bits
|
||||
cdr(1).io.tld.valid -> cdr(1).io.tld.bits
|
||||
))
|
||||
assert( ~(cdr(0).io.tld.valid & cdr(1).io.tld.valid), "Assert Failed! Two CDR can never resp at the same cycle!" )
|
||||
|
||||
cdr(0).io.tld.ready := bus.d.ready
|
||||
cdr(1).io.tld.ready := bus.d.ready
|
||||
|
||||
|
||||
val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
|
||||
val tld = new DecoupledIO(new TLBundleD(edge.bundle))
|
||||
|
||||
}
|
||||
165
src/main/scala/backBoard/pico/BackSystem.scala
Normal file
165
src/main/scala/backBoard/pico/BackSystem.scala
Normal file
@@ -0,0 +1,165 @@
|
||||
package BACK
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
import org.chipsalliance.cde.config._
|
||||
|
||||
abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
|
||||
abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
|
||||
|
||||
case object BackParamsKey extends Field[BackSetting]
|
||||
|
||||
|
||||
|
||||
|
||||
case class BackSetting(
|
||||
){
|
||||
|
||||
}
|
||||
|
||||
trait HasBackParameters {
|
||||
implicit val p: Parameters
|
||||
|
||||
val backSetting = p(BackParamsKey)
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameters {
|
||||
|
||||
val coreClientNode = TLClientNode(Seq(TLMasterPortParameters.v1(
|
||||
Seq(TLMasterParameters.v1(
|
||||
name = "core",
|
||||
sourceId = IdRange(0, 1),
|
||||
))
|
||||
)))
|
||||
|
||||
val cdrNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
|
||||
managers = Seq(TLSlaveParameters.v1(
|
||||
address = Seq(AddressSet(0x40000000L, 0xffL)),
|
||||
regionType = RegionType.UNCACHED,
|
||||
executable = true,
|
||||
supportsGet = TransferSizes(32/8, 32/8),
|
||||
supportsPutFull = TransferSizes(32/8, 32/8),
|
||||
supportsPutPartial = TransferSizes(32/8, 32/8)
|
||||
)),
|
||||
beatBytes = 32/8)))
|
||||
|
||||
val sram = LazyModule(new TLRAM(
|
||||
address = Seq(AddressSet(0x80000000L, 0xffffL)),
|
||||
cacheable = false,
|
||||
executable = true,
|
||||
atomics = false,
|
||||
beatBytes = 4,
|
||||
ecc = ECCParams(),
|
||||
sramReg = false, // drive SRAM data output directly into a register => 1 cycle longer response
|
||||
))
|
||||
|
||||
|
||||
val uart = LazyModule( new TLUART(
|
||||
busWidthBytes = 4,
|
||||
c = UARTParams(
|
||||
address = BigInt(0x50000000L),
|
||||
initBaudRate = BigInt(115200),
|
||||
divinit = 0
|
||||
)) )
|
||||
|
||||
val gpio = LazyModule(new TLGPIO(busWidthBytes = 4, c = GPIOParams(
|
||||
address = BigInt(0x60000000L),
|
||||
width = 16,
|
||||
)))
|
||||
|
||||
val xbar = TLXbar()
|
||||
xbar := coreClientNode
|
||||
cdrNode := xbar
|
||||
sram := xbar
|
||||
uart := xbar
|
||||
gpio := xbar
|
||||
|
||||
|
||||
|
||||
|
||||
lazy val module: BackSysImp = new BackSysImp(this)
|
||||
}
|
||||
|
||||
class BackSysImp(outer: BackSubSys) extends LazyModuleImp(outer) with HasBackParameters {
|
||||
class BackSubSysIO extends Bundle{
|
||||
val overCLK = Input(Bool())
|
||||
val uDatIn = Input(Bool())
|
||||
val uDatOut = Output(Bool())
|
||||
val dDatIn = Input(Bool())
|
||||
val dDatOut = Output(Bool())
|
||||
}
|
||||
|
||||
val ( core_bus, core_edge ) = outer.coreClientNode.out.head
|
||||
val ( cdr_bus, cdr_edge ) = outer.cdrNode.in.head
|
||||
|
||||
|
||||
val io: BackSubSysIO = IO(new BackSubSysIO)
|
||||
|
||||
val pico = Module(new Picorv32_tl(edge = core_edge))
|
||||
val cdr = for( i <- 0 until 2 ) yield { Module(new TLCDR(cdr_edge)) }
|
||||
|
||||
// val trap = Output(Bool())
|
||||
pico.io.irq := 0.U
|
||||
// val eoi = Output(UInt(32.W))
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
cdr(0).io.overCLK := io.overCLK
|
||||
cdr(1).io.overCLK := io.overCLK
|
||||
|
||||
cdr(0).io.datIn := io.uDatIn
|
||||
io.uDatOut := cdr(0).io.uDatOut
|
||||
cdr(1).io.datIn := io.dDatIn
|
||||
io.dDatOut := cdr(1).io.uDatOut
|
||||
|
||||
|
||||
pico.io.tld.bits := core_bus.d.bits
|
||||
pico.io.tld.valid := core_bus.d.valid
|
||||
core_bus.d.ready := pico.io.tld.ready
|
||||
core_bus.a.valid := pico.io.tla.valid
|
||||
core_bus.a.bits := pico.io.tla.bits
|
||||
pico.io.tla.ready := core_bus.a.ready
|
||||
|
||||
|
||||
|
||||
|
||||
cdr(0).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.address(7) === "h0".U
|
||||
cdr(1).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.address(7) === "h1".U
|
||||
cdr(0).io.tla.bits := cdr_bus.a.bits
|
||||
cdr_bus.a.ready :=
|
||||
(cdr_bus.a.address(7) === "h0".U & cdr(0).io.tla.ready) |
|
||||
(cdr_bus.a.address(7) === "h1".U & cdr(1).io.tla.ready)
|
||||
|
||||
cdr_bus.d.valid := cdr(0).io.tld.valid | cdr(1).io.tld.valid
|
||||
cdr_bus.d.bits := Mux1H(Seq(
|
||||
cdr(0).io.tld.valid -> cdr(0).io.tld.bits
|
||||
cdr(1).io.tld.valid -> cdr(1).io.tld.bits
|
||||
))
|
||||
assert( ~(cdr(0).io.tld.valid & cdr(1).io.tld.valid), "Assert Failed! Two CDR can never resp at the same cycle!" )
|
||||
|
||||
cdr(0).io.tld.ready := cdr_bus.d.ready
|
||||
cdr(1).io.tld.ready := cdr_bus.d.ready
|
||||
|
||||
|
||||
|
||||
|
||||
}
|
||||
76
src/main/scala/backBoard/pico/Picorv32_tl.scala
Normal file
76
src/main/scala/backBoard/pico/Picorv32_tl.scala
Normal file
@@ -0,0 +1,76 @@
|
||||
package BACK
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
|
||||
class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule {
|
||||
val io = IO(new Bundle {
|
||||
|
||||
val trap = Output(Bool())
|
||||
|
||||
val tla = new DecoupledIO(new TLBundleA(edge.bundle))
|
||||
val tld = Flipped(new DecoupledIO(new TLBundleD(edge.bundle)))
|
||||
|
||||
val irq = Input(UInt(32.W))
|
||||
val eoi = Output(UInt(32.W))
|
||||
|
||||
})
|
||||
|
||||
|
||||
val core = Module(new Picorv32)
|
||||
|
||||
core.io.clk := clock.asBool
|
||||
core.io.resetn := ~reset.asBool
|
||||
io.trap := core.io.trap
|
||||
|
||||
core.io.pcpi_wr := false.B
|
||||
core.io.pcpi_rd := 0.U
|
||||
core.io.pcpi_wait := false.B
|
||||
core.io.pcpi_ready := true.B
|
||||
|
||||
core.io.irq := io.irq
|
||||
io.eoi := core.io.eoi
|
||||
|
||||
val tlStateNext = Wire( UInt(2.W) )
|
||||
val tlStateCurr = RegNext(tlStateNext, 0.U)
|
||||
|
||||
tlStateNext := Mux1H(Seq(
|
||||
(tlStateCurr === 0.U) -> Mux( core.io.mem_valid, 1.U, 0.U ), //IDLE
|
||||
(tlStateCurr === 1.U) -> Mux( io.tla.fire, 2.U, 1.U ), //A FIRE
|
||||
(tlStateCurr === 2.U) -> Mux( io.tld.fire, 0.U, 2.U ), //D FIRE
|
||||
))
|
||||
|
||||
val tlaValid = RegInit(false.B)
|
||||
|
||||
when( io.tlaClient.fire ){
|
||||
tlaValid := false.B
|
||||
} .elsewhen( tlStateCurr === 0.U & tlStateNext === 1.U ){
|
||||
tlaValid := true.B
|
||||
}
|
||||
|
||||
core.io.mem_ready := io.tld.fire
|
||||
core.io.mem_rdata := io.tld.bits.data
|
||||
io.tld.ready := true.B
|
||||
|
||||
when( core.io.mem_wstrb.orR ){
|
||||
io.tla.bits :=
|
||||
edge.Put(
|
||||
fromSource = 0.U,
|
||||
toAddress = core.io.mem_addr,
|
||||
lgSize = log2Ceil(32/8).U,
|
||||
data = core.io.mem_wdata,
|
||||
mask = core.io.mem_wstrb
|
||||
)._2
|
||||
} .otherwise{
|
||||
io.tla.bits :=
|
||||
edge.Get(
|
||||
fromSource = 0.U,
|
||||
toAddress = core.io.mem_addr,
|
||||
lgSize = log2Ceil(32/8).U
|
||||
)._2
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -50,53 +50,4 @@ class Picorv32 extends BlackBox() with HasBlackBoxResource {
|
||||
addResource("./picorv32.v")
|
||||
}
|
||||
|
||||
class picorv32_tl extends Module{
|
||||
val io = IO(new Bundle {
|
||||
|
||||
val trap = Output(Bool())
|
||||
|
||||
val mem_valid = Output(Bool())
|
||||
val mem_instr = Output(Bool())
|
||||
val mem_ready = Input(Bool())
|
||||
|
||||
val mem_addr = Output(UInt(32.W))
|
||||
val mem_wdata = Output(UInt(32.W))
|
||||
val mem_wstrb = Output(UInt(4.W))
|
||||
val mem_rdata = Input(UInt(32.W))
|
||||
|
||||
|
||||
// IRQ Interface
|
||||
val irq = Input(UInt(32.W))
|
||||
val eoi = Output(UInt(32.W))
|
||||
|
||||
})
|
||||
|
||||
|
||||
val core = Module(new Picorv32)
|
||||
|
||||
core.io.clk := clock.asBool
|
||||
core.io.resetn := ~reset.asBool
|
||||
io.trap := core.io.trap
|
||||
|
||||
io.mem_valid := core.io.mem_valid
|
||||
io.mem_instr := core.io.mem_instr
|
||||
core.io.mem_ready := io.mem_ready
|
||||
|
||||
io.mem_addr := core.io.mem_addr
|
||||
io.mem_wdata:= core.io.mem_wdata
|
||||
io.mem_wstrb:= core.io.mem_wstrb
|
||||
core.io.mem_rdata := io.mem_rdata
|
||||
|
||||
|
||||
|
||||
// Pico Co-Processor Interface (PCPI)
|
||||
core.io.pcpi_wr := false.B
|
||||
core.io.pcpi_rd := 0.U
|
||||
core.io.pcpi_wait := false.B
|
||||
core.io.pcpi_ready := true.B
|
||||
|
||||
// IRQ Interface
|
||||
core.io.irq := io.irq
|
||||
io.eoi := core.io.eoi
|
||||
|
||||
}
|
||||
|
||||
@@ -46,16 +46,19 @@ object testModule extends App {
|
||||
// ChiselGeneratorAnnotation(() => { new CDRIn })
|
||||
// ))
|
||||
|
||||
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
|
||||
ChiselGeneratorAnnotation(() => { new ShinMst })
|
||||
))
|
||||
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
|
||||
// ChiselGeneratorAnnotation(() => { new ShinMst })
|
||||
// ))
|
||||
|
||||
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
|
||||
// ChiselGeneratorAnnotation(() => { new ShinSlvBase })
|
||||
// ))
|
||||
|
||||
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
|
||||
ChiselGeneratorAnnotation(() => { new ShinSlvBase })
|
||||
ChiselGeneratorAnnotation(() => { new picorv32_tl })
|
||||
))
|
||||
|
||||
|
||||
|
||||
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
|
||||
// ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
|
||||
// ))
|
||||
|
||||
Reference in New Issue
Block a user