ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

代码堆完，开始编译

Browse Source
This commit is contained in:
RuigeLee
2024-10-25 14:37:08 +08:00
parent d1ce60daaf
commit a751d34247
6 changed files with 274 additions and 661 deletions
Download Patch File Download Diff File Expand all files Collapse all files

491
src/main/resources/picorv32.v
View File

@@ -29,19 +29,20 @@
// `define DEBUGASM // `define DEBUGASM
// `define DEBUG // `define DEBUG
`ifdef DEBUG `ifndef PICORV32_REGS
`define debug(debug_command) debug_command `define PICORV32_REGS picosoc_regs
`else
`define debug(debug_command)
`endif `endif
`ifdef DEBUGNETS
`define FORMAL_KEEP (* keep *) `define debug(debug_command)
`else
`define FORMAL_KEEP
`endif
`define assert(assert_expr) empty_statement
`define FORMAL_KEEP
`define assert(assert_expr) empty_statement
// uncomment this for register file in extra module // uncomment this for register file in extra module
@@ -808,17 +809,6 @@ module picorv32 #(
end end
`endif `endif
`ifdef DEBUG
always @(posedge clk) begin
if (dbg_next) begin
if (&dbg_insn_opcode[1:0])
$display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
else
$display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
end
end
`endif
always @(posedge clk) begin always @(posedge clk) begin
is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal}; is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub}; is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
@@ -2270,454 +2260,21 @@ module picorv32_pcpi_div (
end end
endmodule endmodule
module picosoc_regs (
/*************************************************************** input clk, wen,
* picorv32_axi input [5:0] waddr,
***************************************************************/ input [5:0] raddr1,
input [5:0] raddr2,
module picorv32_axi #( input [31:0] wdata,
parameter [ 0:0] ENABLE_COUNTERS = 1, output [31:0] rdata1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1, output [31:0] rdata2
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
input clk, resetn,
output trap,
// AXI4-lite master memory interface
output mem_axi_awvalid,
input mem_axi_awready,
output [31:0] mem_axi_awaddr,
output [ 2:0] mem_axi_awprot,
output mem_axi_wvalid,
input mem_axi_wready,
output [31:0] mem_axi_wdata,
output [ 3:0] mem_axi_wstrb,
input mem_axi_bvalid,
output mem_axi_bready,
output mem_axi_arvalid,
input mem_axi_arready,
output [31:0] mem_axi_araddr,
output [ 2:0] mem_axi_arprot,
input mem_axi_rvalid,
output mem_axi_rready,
input [31:0] mem_axi_rdata,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
// Trace Interface
output trace_valid,
output [35:0] trace_data
); );
wire mem_valid; reg [31:0] regs [0:31];
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_rdata;
picorv32_axi_adapter axi_adapter ( always @(posedge clk)
.clk (clk ), if (wen) regs[waddr[4:0]] <= wdata;
.resetn (resetn ),
.mem_axi_awvalid(mem_axi_awvalid),
.mem_axi_awready(mem_axi_awready),
.mem_axi_awaddr (mem_axi_awaddr ),
.mem_axi_awprot (mem_axi_awprot ),
.mem_axi_wvalid (mem_axi_wvalid ),
.mem_axi_wready (mem_axi_wready ),
.mem_axi_wdata (mem_axi_wdata ),
.mem_axi_wstrb (mem_axi_wstrb ),
.mem_axi_bvalid (mem_axi_bvalid ),
.mem_axi_bready (mem_axi_bready ),
.mem_axi_arvalid(mem_axi_arvalid),
.mem_axi_arready(mem_axi_arready),
.mem_axi_araddr (mem_axi_araddr ),
.mem_axi_arprot (mem_axi_arprot ),
.mem_axi_rvalid (mem_axi_rvalid ),
.mem_axi_rready (mem_axi_rready ),
.mem_axi_rdata (mem_axi_rdata ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
picorv32 #( assign rdata1 = regs[raddr1[4:0]];
.ENABLE_COUNTERS (ENABLE_COUNTERS ), assign rdata2 = regs[raddr2[4:0]];
.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
.BARREL_SHIFTER (BARREL_SHIFTER ),
.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
.COMPRESSED_ISA (COMPRESSED_ISA ),
.CATCH_MISALIGN (CATCH_MISALIGN ),
.CATCH_ILLINSN (CATCH_ILLINSN ),
.ENABLE_PCPI (ENABLE_PCPI ),
.ENABLE_MUL (ENABLE_MUL ),
.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
.ENABLE_DIV (ENABLE_DIV ),
.ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.ENABLE_TRACE (ENABLE_TRACE ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ),
.PROGADDR_IRQ (PROGADDR_IRQ ),
.STACKADDR (STACKADDR )
) picorv32_core (
.clk (clk ),
.resetn (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
.trace_valid(trace_valid),
.trace_data (trace_data)
);
endmodule endmodule
/***************************************************************
* picorv32_axi_adapter
***************************************************************/
module picorv32_axi_adapter (
input clk, resetn,
// AXI4-lite master memory interface
output mem_axi_awvalid,
input mem_axi_awready,
output [31:0] mem_axi_awaddr,
output [ 2:0] mem_axi_awprot,
output mem_axi_wvalid,
input mem_axi_wready,
output [31:0] mem_axi_wdata,
output [ 3:0] mem_axi_wstrb,
input mem_axi_bvalid,
output mem_axi_bready,
output mem_axi_arvalid,
input mem_axi_arready,
output [31:0] mem_axi_araddr,
output [ 2:0] mem_axi_arprot,
input mem_axi_rvalid,
output mem_axi_rready,
input [31:0] mem_axi_rdata,
// Native PicoRV32 memory interface
input mem_valid,
input mem_instr,
output mem_ready,
input [31:0] mem_addr,
input [31:0] mem_wdata,
input [ 3:0] mem_wstrb,
output [31:0] mem_rdata
);
reg ack_awvalid;
reg ack_arvalid;
reg ack_wvalid;
reg xfer_done;
assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
assign mem_axi_awaddr = mem_addr;
assign mem_axi_awprot = 0;
assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid;
assign mem_axi_araddr = mem_addr;
assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;
assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid;
assign mem_axi_wdata = mem_wdata;
assign mem_axi_wstrb = mem_wstrb;
assign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
assign mem_axi_bready = mem_valid && |mem_wstrb;
assign mem_axi_rready = mem_valid && !mem_wstrb;
assign mem_rdata = mem_axi_rdata;
always @(posedge clk) begin
if (!resetn) begin
ack_awvalid <= 0;
end else begin
xfer_done <= mem_valid && mem_ready;
if (mem_axi_awready && mem_axi_awvalid)
ack_awvalid <= 1;
if (mem_axi_arready && mem_axi_arvalid)
ack_arvalid <= 1;
if (mem_axi_wready && mem_axi_wvalid)
ack_wvalid <= 1;
if (xfer_done || !mem_valid) begin
ack_awvalid <= 0;
ack_arvalid <= 0;
ack_wvalid <= 0;
end
end
end
endmodule
/***************************************************************
* picorv32_wb
***************************************************************/
module picorv32_wb #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
output trap,
// Wishbone interfaces
input wb_rst_i,
input wb_clk_i,
output reg [31:0] wbm_adr_o,
output reg [31:0] wbm_dat_o,
input [31:0] wbm_dat_i,
output reg wbm_we_o,
output reg [3:0] wbm_sel_o,
output reg wbm_stb_o,
input wbm_ack_i,
output reg wbm_cyc_o,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
// Trace Interface
output trace_valid,
output [35:0] trace_data,
output mem_instr
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
reg mem_ready;
reg [31:0] mem_rdata;
wire clk;
wire resetn;
assign clk = wb_clk_i;
assign resetn = ~wb_rst_i;
picorv32 #(
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
.BARREL_SHIFTER (BARREL_SHIFTER ),
.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
.COMPRESSED_ISA (COMPRESSED_ISA ),
.CATCH_MISALIGN (CATCH_MISALIGN ),
.CATCH_ILLINSN (CATCH_ILLINSN ),
.ENABLE_PCPI (ENABLE_PCPI ),
.ENABLE_MUL (ENABLE_MUL ),
.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
.ENABLE_DIV (ENABLE_DIV ),
.ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.ENABLE_TRACE (ENABLE_TRACE ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ),
.PROGADDR_IRQ (PROGADDR_IRQ ),
.STACKADDR (STACKADDR )
) picorv32_core (
.clk (clk ),
.resetn (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
.trace_valid(trace_valid),
.trace_data (trace_data)
);
localparam IDLE = 2'b00;
localparam WBSTART = 2'b01;
localparam WBEND = 2'b10;
reg [1:0] state;
wire we;
assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wbm_adr_o <= 0;
wbm_dat_o <= 0;
wbm_we_o <= 0;
wbm_sel_o <= 0;
wbm_stb_o <= 0;
wbm_cyc_o <= 0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
if (mem_valid) begin
wbm_adr_o <= mem_addr;
wbm_dat_o <= mem_wdata;
wbm_we_o <= we;
wbm_sel_o <= mem_wstrb;
wbm_stb_o <= 1'b1;
wbm_cyc_o <= 1'b1;
state <= WBSTART;
end else begin
mem_ready <= 1'b0;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBSTART:begin
if (wbm_ack_i) begin
mem_rdata <= wbm_dat_i;
mem_ready <= 1'b1;
state <= WBEND;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBEND: begin
mem_ready <= 1'b0;
state <= IDLE;
end
default:
state <= IDLE;
endcase
end
end
endmodule

139
src/main/scala/backBoard/pico/BackSubSystem.scala
View File

@@ -1,139 +0,0 @@
package BACK
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
case object BackParamsKey extends Field[BackSetting]
case class BackSetting(
){
}
trait HasBackParameters {
implicit val p: Parameters
val backSetting = p(BackParamsKey)
}
class BackSubSys( )(implicit p: Parameters) extends LazyModule with HasBackParameters {
class AXI4MasterNode(portParams: Seq[AXI4MasterPortParameters])
val AXI4SlaveNode(portParams: Seq[AXI4SlavePortParameters])
val cdrNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
managers = Seq(TLSlaveParameters.v1(
address = Seq(AddressSet(0x40000000L, 0xffL)),
regionType = RegionType.UNCACHED,
executable = true,
supportsGet = TransferSizes(32/8, 32/8),
supportsPutFull = TransferSizes(32/8, 32/8),
supportsPutPartial = TransferSizes(32/8, 32/8)
)),
beatBytes = 32/8)))
val sram = LazyModule(new AXI4RAM(
address = Seq(AddressSet(0x80000000L, 0xffffL)),
cacheable = false,
executable = true,
beatBytes = 4,
devName = Some("SRAM"),
wcorrupt = false))
val uart = LazyModule( new UART(
busWidthBytes = 4,
c = UARTParams(
address = BigInt(0x50000000L),
initBaudRate = BigInt(115200),
)) )
val gpio = LazyModule(new GPIO(busWidthBytes = 4, c = GPIOParams(
address = BigInt(0x60000000L),
width = 16,
)))
lazy val module: BackSubSysImp = new BackSubSysImp(this)
}
class BackSubSysImp(outer: BackSubSys) extends LazyModuleImp(outer) with HasBackParameters {
class BackSubSysIO extends Bundle{
val overCLK = Input(Bool())
val uDatIn = Input(Bool())
val uDatOut = Output(Bool())
val dDatIn = Input(Bool())
val dDatOut = Output(Bool())
}
val ( bus, edge ) = chipLinkMasterNode.in.head
val io: BackSubSysIO = IO(new BackSubSysIO)
val cdr = for( i <- 0 until 2 ) yield { Module(new TLCDR(edge)) }
cdr(0).io.overCLK := io.overCLK
cdr(1).io.overCLK := io.overCLK
cdr(0).io.datIn := io.uDatIn
io.uDatOut := cdr(0).io.uDatOut
cdr(1).io.datIn := io.dDatIn
io.dDatOut := cdr(1).io.uDatOut
cdr(0).io.tla.valid := bus.a.valid & bus.a.address(7) === "h0".U
cdr(1).io.tla.valid := bus.a.valid & bus.a.address(7) === "h1".U
cdr(0).io.tla.bits := bus.a.bits
bus.a.ready :=
(bus.a.address(7) === "h0".U & cdr(0).io.tla.ready) |
(bus.a.address(7) === "h1".U & cdr(1).io.tla.ready)
bus.d.valid := cdr(0).io.tld.valid | cdr(1).io.tld.valid
bus.d.bits := Mux1H(Seq(
cdr(0).io.tld.valid -> cdr(0).io.tld.bits
cdr(1).io.tld.valid -> cdr(1).io.tld.bits
))
assert( ~(cdr(0).io.tld.valid & cdr(1).io.tld.valid), "Assert Failed! Two CDR can never resp at the same cycle!" )
cdr(0).io.tld.ready := bus.d.ready
cdr(1).io.tld.ready := bus.d.ready
val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
val tld = new DecoupledIO(new TLBundleD(edge.bundle))
}

165
src/main/scala/backBoard/pico/BackSystem.scala Normal file
View File

@@ -0,0 +1,165 @@
package BACK
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
case object BackParamsKey extends Field[BackSetting]
case class BackSetting(
){
}
trait HasBackParameters {
implicit val p: Parameters
val backSetting = p(BackParamsKey)
}
class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameters {
val coreClientNode = TLClientNode(Seq(TLMasterPortParameters.v1(
Seq(TLMasterParameters.v1(
name = "core",
sourceId = IdRange(0, 1),
))
)))
val cdrNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
managers = Seq(TLSlaveParameters.v1(
address = Seq(AddressSet(0x40000000L, 0xffL)),
regionType = RegionType.UNCACHED,
executable = true,
supportsGet = TransferSizes(32/8, 32/8),
supportsPutFull = TransferSizes(32/8, 32/8),
supportsPutPartial = TransferSizes(32/8, 32/8)
)),
beatBytes = 32/8)))
val sram = LazyModule(new TLRAM(
address = Seq(AddressSet(0x80000000L, 0xffffL)),
cacheable = false,
executable = true,
atomics = false,
beatBytes = 4,
ecc = ECCParams(),
sramReg = false, // drive SRAM data output directly into a register => 1 cycle longer response
))
val uart = LazyModule( new TLUART(
busWidthBytes = 4,
c = UARTParams(
address = BigInt(0x50000000L),
initBaudRate = BigInt(115200),
divinit = 0
)) )
val gpio = LazyModule(new TLGPIO(busWidthBytes = 4, c = GPIOParams(
address = BigInt(0x60000000L),
width = 16,
)))
val xbar = TLXbar()
xbar := coreClientNode
cdrNode := xbar
sram := xbar
uart := xbar
gpio := xbar
lazy val module: BackSysImp = new BackSysImp(this)
}
class BackSysImp(outer: BackSubSys) extends LazyModuleImp(outer) with HasBackParameters {
class BackSubSysIO extends Bundle{
val overCLK = Input(Bool())
val uDatIn = Input(Bool())
val uDatOut = Output(Bool())
val dDatIn = Input(Bool())
val dDatOut = Output(Bool())
}
val ( core_bus, core_edge ) = outer.coreClientNode.out.head
val ( cdr_bus, cdr_edge ) = outer.cdrNode.in.head
val io: BackSubSysIO = IO(new BackSubSysIO)
val pico = Module(new Picorv32_tl(edge = core_edge))
val cdr = for( i <- 0 until 2 ) yield { Module(new TLCDR(cdr_edge)) }
// val trap = Output(Bool())
pico.io.irq := 0.U
// val eoi = Output(UInt(32.W))
cdr(0).io.overCLK := io.overCLK
cdr(1).io.overCLK := io.overCLK
cdr(0).io.datIn := io.uDatIn
io.uDatOut := cdr(0).io.uDatOut
cdr(1).io.datIn := io.dDatIn
io.dDatOut := cdr(1).io.uDatOut
pico.io.tld.bits := core_bus.d.bits
pico.io.tld.valid := core_bus.d.valid
core_bus.d.ready := pico.io.tld.ready
core_bus.a.valid := pico.io.tla.valid
core_bus.a.bits := pico.io.tla.bits
pico.io.tla.ready := core_bus.a.ready
cdr(0).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.address(7) === "h0".U
cdr(1).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.address(7) === "h1".U
cdr(0).io.tla.bits := cdr_bus.a.bits
cdr_bus.a.ready :=
(cdr_bus.a.address(7) === "h0".U & cdr(0).io.tla.ready) |
(cdr_bus.a.address(7) === "h1".U & cdr(1).io.tla.ready)
cdr_bus.d.valid := cdr(0).io.tld.valid | cdr(1).io.tld.valid
cdr_bus.d.bits := Mux1H(Seq(
cdr(0).io.tld.valid -> cdr(0).io.tld.bits
cdr(1).io.tld.valid -> cdr(1).io.tld.bits
))
assert( ~(cdr(0).io.tld.valid & cdr(1).io.tld.valid), "Assert Failed! Two CDR can never resp at the same cycle!" )
cdr(0).io.tld.ready := cdr_bus.d.ready
cdr(1).io.tld.ready := cdr_bus.d.ready
}

76
src/main/scala/backBoard/pico/Picorv32_tl.scala Normal file
View File

@@ -0,0 +1,76 @@
package BACK
import chisel3._
import chisel3.util._
class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule {
val io = IO(new Bundle {
val trap = Output(Bool())
val tla = new DecoupledIO(new TLBundleA(edge.bundle))
val tld = Flipped(new DecoupledIO(new TLBundleD(edge.bundle)))
val irq = Input(UInt(32.W))
val eoi = Output(UInt(32.W))
})
val core = Module(new Picorv32)
core.io.clk := clock.asBool
core.io.resetn := ~reset.asBool
io.trap := core.io.trap
core.io.pcpi_wr := false.B
core.io.pcpi_rd := 0.U
core.io.pcpi_wait := false.B
core.io.pcpi_ready := true.B
core.io.irq := io.irq
io.eoi := core.io.eoi
val tlStateNext = Wire( UInt(2.W) )
val tlStateCurr = RegNext(tlStateNext, 0.U)
tlStateNext := Mux1H(Seq(
(tlStateCurr === 0.U) -> Mux( core.io.mem_valid, 1.U, 0.U ), //IDLE
(tlStateCurr === 1.U) -> Mux( io.tla.fire, 2.U, 1.U ), //A FIRE
(tlStateCurr === 2.U) -> Mux( io.tld.fire, 0.U, 2.U ), //D FIRE
))
val tlaValid = RegInit(false.B)
when( io.tlaClient.fire ){
tlaValid := false.B
} .elsewhen( tlStateCurr === 0.U & tlStateNext === 1.U ){
tlaValid := true.B
}
core.io.mem_ready := io.tld.fire
core.io.mem_rdata := io.tld.bits.data
io.tld.ready := true.B
when( core.io.mem_wstrb.orR ){
io.tla.bits :=
edge.Put(
fromSource = 0.U,
toAddress = core.io.mem_addr,
lgSize = log2Ceil(32/8).U,
data = core.io.mem_wdata,
mask = core.io.mem_wstrb
)._2
} .otherwise{
io.tla.bits :=
edge.Get(
fromSource = 0.U,
toAddress = core.io.mem_addr,
lgSize = log2Ceil(32/8).U
)._2
}
}

49
src/main/scala/backBoard/pico/picorv32.scala
View File

@@ -50,53 +50,4 @@ class Picorv32 extends BlackBox() with HasBlackBoxResource {
addResource("./picorv32.v") addResource("./picorv32.v")
} }
class picorv32_tl extends Module{
val io = IO(new Bundle {
val trap = Output(Bool())
val mem_valid = Output(Bool())
val mem_instr = Output(Bool())
val mem_ready = Input(Bool())
val mem_addr = Output(UInt(32.W))
val mem_wdata = Output(UInt(32.W))
val mem_wstrb = Output(UInt(4.W))
val mem_rdata = Input(UInt(32.W))
// IRQ Interface
val irq = Input(UInt(32.W))
val eoi = Output(UInt(32.W))
})
val core = Module(new Picorv32)
core.io.clk := clock.asBool
core.io.resetn := ~reset.asBool
io.trap := core.io.trap
io.mem_valid := core.io.mem_valid
io.mem_instr := core.io.mem_instr
core.io.mem_ready := io.mem_ready
io.mem_addr := core.io.mem_addr
io.mem_wdata:= core.io.mem_wdata
io.mem_wstrb:= core.io.mem_wstrb
core.io.mem_rdata := io.mem_rdata
// Pico Co-Processor Interface (PCPI)
core.io.pcpi_wr := false.B
core.io.pcpi_rd := 0.U
core.io.pcpi_wait := false.B
core.io.pcpi_ready := true.B
// IRQ Interface
core.io.irq := io.irq
io.eoi := core.io.eoi
}

13
src/test/scala/gcd/test.scala
View File

@@ -46,16 +46,19 @@ object testModule extends App {
// ChiselGeneratorAnnotation(() => { new CDRIn }) // ChiselGeneratorAnnotation(() => { new CDRIn })
// )) // ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new ShinMst }) // ChiselGeneratorAnnotation(() => { new ShinMst })
)) // ))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new ShinSlvBase })
// ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new ShinSlvBase }) ChiselGeneratorAnnotation(() => { new picorv32_tl })
)) ))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq( // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new BackPlaneChainTest }) // ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
// )) // ))