ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

代码堆完，开始编译

Browse Source
This commit is contained in:
RuigeLee
2024-10-25 14:37:08 +08:00
parent d1ce60daaf
commit a751d34247
6 changed files with 274 additions and 661 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/test/scala/gcd/test.scala
View File

@@ -46,16 +46,19 @@ object testModule extends App {
// ChiselGeneratorAnnotation(() => { new CDRIn })
// ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new ShinMst })
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new ShinMst })
// ))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new ShinSlvBase })
// ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new ShinSlvBase })
ChiselGeneratorAnnotation(() => { new picorv32_tl })
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
// ))