代码堆完，开始编译

src/main/scala/backBoard/pico/picorv32.scala

@@ -10,7 +10,7 @@ import chisel3.experimental._
 class Picorv32 extends BlackBox() with HasBlackBoxResource {
   val io = IO(new Bundle {
 	val clk = Input(Bool())
-    val resetn = Input(Bool())
+  val resetn = Input(Bool())
 	val trap = Output(Bool())
 
 	val mem_valid = Output(Bool())
@@ -50,53 +50,4 @@ class Picorv32 extends BlackBox() with HasBlackBoxResource {
   addResource("./picorv32.v")
 }
 
-class picorv32_tl extends Module{
-  val io = IO(new Bundle {
 
-    val trap = Output(Bool())
-
-    val mem_valid = Output(Bool())
-    val mem_instr = Output(Bool())
-    val mem_ready = Input(Bool())
-
-    val mem_addr  = Output(UInt(32.W))
-    val mem_wdata = Output(UInt(32.W))
-    val mem_wstrb = Output(UInt(4.W))
-    val mem_rdata = Input(UInt(32.W))
-
-
-    // IRQ Interface
-    val irq = Input(UInt(32.W))
-    val eoi = Output(UInt(32.W))
-
-  })
-
-
-  val core = Module(new Picorv32)
-
-	core.io.clk := clock.asBool
-  core.io.resetn := ~reset.asBool
-	io.trap := core.io.trap 
-
-	io.mem_valid := core.io.mem_valid
-	io.mem_instr := core.io.mem_instr
-	core.io.mem_ready := io.mem_ready
-
-	io.mem_addr := core.io.mem_addr
-	io.mem_wdata:= core.io.mem_wdata
-	io.mem_wstrb:= core.io.mem_wstrb
-	core.io.mem_rdata := io.mem_rdata
-
-
-
-	// Pico Co-Processor Interface (PCPI)
-	core.io.pcpi_wr    := false.B
-	core.io.pcpi_rd    := 0.U
-	core.io.pcpi_wait  := false.B
-	core.io.pcpi_ready := true.B
-
-	// IRQ Interface
-	core.io.irq := io.irq
-	io.eoi := core.io.eoi
-
-}