ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

代码堆完，开始编译

Browse Source
This commit is contained in:
RuigeLee
2024-10-25 14:37:08 +08:00
parent d1ce60daaf
commit a751d34247
6 changed files with 274 additions and 661 deletions
Download Patch File Download Diff File Expand all files Collapse all files

139
src/main/scala/backBoard/pico/BackSubSystem.scala
View File

@@ -1,139 +0,0 @@
package BACK
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
case object BackParamsKey extends Field[BackSetting]
case class BackSetting(
){
}
trait HasBackParameters {
implicit val p: Parameters
val backSetting = p(BackParamsKey)
}
class BackSubSys( )(implicit p: Parameters) extends LazyModule with HasBackParameters {
class AXI4MasterNode(portParams: Seq[AXI4MasterPortParameters])
val AXI4SlaveNode(portParams: Seq[AXI4SlavePortParameters])
val cdrNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
managers = Seq(TLSlaveParameters.v1(
address = Seq(AddressSet(0x40000000L, 0xffL)),
regionType = RegionType.UNCACHED,
executable = true,
supportsGet = TransferSizes(32/8, 32/8),
supportsPutFull = TransferSizes(32/8, 32/8),
supportsPutPartial = TransferSizes(32/8, 32/8)
)),
beatBytes = 32/8)))
val sram = LazyModule(new AXI4RAM(
address = Seq(AddressSet(0x80000000L, 0xffffL)),
cacheable = false,
executable = true,
beatBytes = 4,
devName = Some("SRAM"),
wcorrupt = false))
val uart = LazyModule( new UART(
busWidthBytes = 4,
c = UARTParams(
address = BigInt(0x50000000L),
initBaudRate = BigInt(115200),
)) )
val gpio = LazyModule(new GPIO(busWidthBytes = 4, c = GPIOParams(
address = BigInt(0x60000000L),
width = 16,
)))
lazy val module: BackSubSysImp = new BackSubSysImp(this)
}
class BackSubSysImp(outer: BackSubSys) extends LazyModuleImp(outer) with HasBackParameters {
class BackSubSysIO extends Bundle{
val overCLK = Input(Bool())
val uDatIn = Input(Bool())
val uDatOut = Output(Bool())
val dDatIn = Input(Bool())
val dDatOut = Output(Bool())
}
val ( bus, edge ) = chipLinkMasterNode.in.head
val io: BackSubSysIO = IO(new BackSubSysIO)
val cdr = for( i <- 0 until 2 ) yield { Module(new TLCDR(edge)) }
cdr(0).io.overCLK := io.overCLK
cdr(1).io.overCLK := io.overCLK
cdr(0).io.datIn := io.uDatIn
io.uDatOut := cdr(0).io.uDatOut
cdr(1).io.datIn := io.dDatIn
io.dDatOut := cdr(1).io.uDatOut
cdr(0).io.tla.valid := bus.a.valid & bus.a.address(7) === "h0".U
cdr(1).io.tla.valid := bus.a.valid & bus.a.address(7) === "h1".U
cdr(0).io.tla.bits := bus.a.bits
bus.a.ready :=
(bus.a.address(7) === "h0".U & cdr(0).io.tla.ready) |
(bus.a.address(7) === "h1".U & cdr(1).io.tla.ready)
bus.d.valid := cdr(0).io.tld.valid | cdr(1).io.tld.valid
bus.d.bits := Mux1H(Seq(
cdr(0).io.tld.valid -> cdr(0).io.tld.bits
cdr(1).io.tld.valid -> cdr(1).io.tld.bits
))
assert( ~(cdr(0).io.tld.valid & cdr(1).io.tld.valid), "Assert Failed! Two CDR can never resp at the same cycle!" )
cdr(0).io.tld.ready := bus.d.ready
cdr(1).io.tld.ready := bus.d.ready
val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
val tld = new DecoupledIO(new TLBundleD(edge.bundle))
}

165
src/main/scala/backBoard/pico/BackSystem.scala Normal file
View File

@@ -0,0 +1,165 @@
package BACK
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
case object BackParamsKey extends Field[BackSetting]
case class BackSetting(
){
}
trait HasBackParameters {
implicit val p: Parameters
val backSetting = p(BackParamsKey)
}
class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameters {
val coreClientNode = TLClientNode(Seq(TLMasterPortParameters.v1(
Seq(TLMasterParameters.v1(
name = "core",
sourceId = IdRange(0, 1),
))
)))
val cdrNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
managers = Seq(TLSlaveParameters.v1(
address = Seq(AddressSet(0x40000000L, 0xffL)),
regionType = RegionType.UNCACHED,
executable = true,
supportsGet = TransferSizes(32/8, 32/8),
supportsPutFull = TransferSizes(32/8, 32/8),
supportsPutPartial = TransferSizes(32/8, 32/8)
)),
beatBytes = 32/8)))
val sram = LazyModule(new TLRAM(
address = Seq(AddressSet(0x80000000L, 0xffffL)),
cacheable = false,
executable = true,
atomics = false,
beatBytes = 4,
ecc = ECCParams(),
sramReg = false, // drive SRAM data output directly into a register => 1 cycle longer response
))
val uart = LazyModule( new TLUART(
busWidthBytes = 4,
c = UARTParams(
address = BigInt(0x50000000L),
initBaudRate = BigInt(115200),
divinit = 0
)) )
val gpio = LazyModule(new TLGPIO(busWidthBytes = 4, c = GPIOParams(
address = BigInt(0x60000000L),
width = 16,
)))
val xbar = TLXbar()
xbar := coreClientNode
cdrNode := xbar
sram := xbar
uart := xbar
gpio := xbar
lazy val module: BackSysImp = new BackSysImp(this)
}
class BackSysImp(outer: BackSubSys) extends LazyModuleImp(outer) with HasBackParameters {
class BackSubSysIO extends Bundle{
val overCLK = Input(Bool())
val uDatIn = Input(Bool())
val uDatOut = Output(Bool())
val dDatIn = Input(Bool())
val dDatOut = Output(Bool())
}
val ( core_bus, core_edge ) = outer.coreClientNode.out.head
val ( cdr_bus, cdr_edge ) = outer.cdrNode.in.head
val io: BackSubSysIO = IO(new BackSubSysIO)
val pico = Module(new Picorv32_tl(edge = core_edge))
val cdr = for( i <- 0 until 2 ) yield { Module(new TLCDR(cdr_edge)) }
// val trap = Output(Bool())
pico.io.irq := 0.U
// val eoi = Output(UInt(32.W))
cdr(0).io.overCLK := io.overCLK
cdr(1).io.overCLK := io.overCLK
cdr(0).io.datIn := io.uDatIn
io.uDatOut := cdr(0).io.uDatOut
cdr(1).io.datIn := io.dDatIn
io.dDatOut := cdr(1).io.uDatOut
pico.io.tld.bits := core_bus.d.bits
pico.io.tld.valid := core_bus.d.valid
core_bus.d.ready := pico.io.tld.ready
core_bus.a.valid := pico.io.tla.valid
core_bus.a.bits := pico.io.tla.bits
pico.io.tla.ready := core_bus.a.ready
cdr(0).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.address(7) === "h0".U
cdr(1).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.address(7) === "h1".U
cdr(0).io.tla.bits := cdr_bus.a.bits
cdr_bus.a.ready :=
(cdr_bus.a.address(7) === "h0".U & cdr(0).io.tla.ready) |
(cdr_bus.a.address(7) === "h1".U & cdr(1).io.tla.ready)
cdr_bus.d.valid := cdr(0).io.tld.valid | cdr(1).io.tld.valid
cdr_bus.d.bits := Mux1H(Seq(
cdr(0).io.tld.valid -> cdr(0).io.tld.bits
cdr(1).io.tld.valid -> cdr(1).io.tld.bits
))
assert( ~(cdr(0).io.tld.valid & cdr(1).io.tld.valid), "Assert Failed! Two CDR can never resp at the same cycle!" )
cdr(0).io.tld.ready := cdr_bus.d.ready
cdr(1).io.tld.ready := cdr_bus.d.ready
}

76
src/main/scala/backBoard/pico/Picorv32_tl.scala Normal file
View File

@@ -0,0 +1,76 @@
package BACK
import chisel3._
import chisel3.util._
class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule {
val io = IO(new Bundle {
val trap = Output(Bool())
val tla = new DecoupledIO(new TLBundleA(edge.bundle))
val tld = Flipped(new DecoupledIO(new TLBundleD(edge.bundle)))
val irq = Input(UInt(32.W))
val eoi = Output(UInt(32.W))
})
val core = Module(new Picorv32)
core.io.clk := clock.asBool
core.io.resetn := ~reset.asBool
io.trap := core.io.trap
core.io.pcpi_wr := false.B
core.io.pcpi_rd := 0.U
core.io.pcpi_wait := false.B
core.io.pcpi_ready := true.B
core.io.irq := io.irq
io.eoi := core.io.eoi
val tlStateNext = Wire( UInt(2.W) )
val tlStateCurr = RegNext(tlStateNext, 0.U)
tlStateNext := Mux1H(Seq(
(tlStateCurr === 0.U) -> Mux( core.io.mem_valid, 1.U, 0.U ), //IDLE
(tlStateCurr === 1.U) -> Mux( io.tla.fire, 2.U, 1.U ), //A FIRE
(tlStateCurr === 2.U) -> Mux( io.tld.fire, 0.U, 2.U ), //D FIRE
))
val tlaValid = RegInit(false.B)
when( io.tlaClient.fire ){
tlaValid := false.B
} .elsewhen( tlStateCurr === 0.U & tlStateNext === 1.U ){
tlaValid := true.B
}
core.io.mem_ready := io.tld.fire
core.io.mem_rdata := io.tld.bits.data
io.tld.ready := true.B
when( core.io.mem_wstrb.orR ){
io.tla.bits :=
edge.Put(
fromSource = 0.U,
toAddress = core.io.mem_addr,
lgSize = log2Ceil(32/8).U,
data = core.io.mem_wdata,
mask = core.io.mem_wstrb
)._2
} .otherwise{
io.tla.bits :=
edge.Get(
fromSource = 0.U,
toAddress = core.io.mem_addr,
lgSize = log2Ceil(32/8).U
)._2
}
}

51
src/main/scala/backBoard/pico/picorv32.scala
View File

@@ -10,7 +10,7 @@ import chisel3.experimental._
class Picorv32 extends BlackBox() with HasBlackBoxResource {
val io = IO(new Bundle {
val clk = Input(Bool())
val resetn = Input(Bool())
val resetn = Input(Bool())
val trap = Output(Bool())
val mem_valid = Output(Bool())
@@ -50,53 +50,4 @@ class Picorv32 extends BlackBox() with HasBlackBoxResource {
addResource("./picorv32.v")
}
class picorv32_tl extends Module{
val io = IO(new Bundle {
val trap = Output(Bool())
val mem_valid = Output(Bool())
val mem_instr = Output(Bool())
val mem_ready = Input(Bool())
val mem_addr = Output(UInt(32.W))
val mem_wdata = Output(UInt(32.W))
val mem_wstrb = Output(UInt(4.W))
val mem_rdata = Input(UInt(32.W))
// IRQ Interface
val irq = Input(UInt(32.W))
val eoi = Output(UInt(32.W))
})
val core = Module(new Picorv32)
core.io.clk := clock.asBool
core.io.resetn := ~reset.asBool
io.trap := core.io.trap
io.mem_valid := core.io.mem_valid
io.mem_instr := core.io.mem_instr
core.io.mem_ready := io.mem_ready
io.mem_addr := core.io.mem_addr
io.mem_wdata:= core.io.mem_wdata
io.mem_wstrb:= core.io.mem_wstrb
core.io.mem_rdata := io.mem_rdata
// Pico Co-Processor Interface (PCPI)
core.io.pcpi_wr := false.B
core.io.pcpi_rd := 0.U
core.io.pcpi_wait := false.B
core.io.pcpi_ready := true.B
// IRQ Interface
core.io.irq := io.irq
io.eoi := core.io.eoi
}