diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 43539e2..0501038 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -222,8 +222,8 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
   val io: InterfaceIO = IO(new InterfaceIO)
 
   val oSpi  = Module(new SSpiInterface)
-  val oQSpi = Module(new QSpiInterface)
-  val iQSpi = Module(new QSpiInterface)
+  val oQSpi = Module(new QSpiInterface(true))
+  val iQSpi = Module(new QSpiInterface(false))
   val aQSpi = Module(new SyncQSpiInterface)
 
   io.ospi <> oSpi.spi
diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala
index 3b40b9f..4609bb2 100644
--- a/src/main/scala/backBoard/shin/SpiInterface.scala
+++ b/src/main/scala/backBoard/shin/SpiInterface.scala
@@ -41,7 +41,8 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
 
 
 
-  val isSckPosedge     = ~shiftSCK(2) & shiftSCK(1)
+  val isSckPosedge     = ~shiftSCK(2) &  shiftSCK(1)
+  val isSckNegedge     =  shiftSCK(2) & ~shiftSCK(1)
   val isSckPosedgeNext = ShiftRegisters(isSckPosedge, 2, false.B, true.B)
 
   val exRego = RegInit(0.U(8.W))
@@ -152,7 +153,7 @@ class SSpiInterface extends SpiInterfaceBase{
 
 }
 
-class QSpiInterface extends SpiInterfaceBase{
+class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
   val qspi = IO(new QSPIInterfaceIO)
   val shiftMOSI = ShiftRegisters(qspi.mosi, 3, 0.U(4.W), true.B)
 
@@ -163,8 +164,16 @@ class QSpiInterface extends SpiInterfaceBase{
 
   
   io.isEnR := 
-             (isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & shiftMOSI(1) === "b1000".U & byteSel === 2.U ) |
-             (isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U)
+    (
+      if(edge){
+        (isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & shiftMOSI(1) === "b1000".U & byteSel === 2.U ) |
+        (isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U)    
+      } else {
+        (isSckNegedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 2.U)    
+      }
+    )
+
+
 
   when( (shiftCSn(2) & ~shiftCSn(1)) || (~shiftCSn(2) & shiftCSn(1)) ){  //CS下跳或上跳
     spiCmd := 0.U
@@ -187,10 +196,13 @@ class QSpiInterface extends SpiInterfaceBase{
     }
   }
 
-  //输出在SCK上升沿准备数据
+  //输出在SCK XX沿准备数据
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
     exRego := 0.U //第一个byte 地址0
-  } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
+  } .elsewhen(
+    (if( edge ) {isSckPosedge} else {isSckNegedge})
+    & ~shiftCSn(1)
+  ){
     when( bitSel.andR ){
       when((byteSel === 0.U || byteSel === 1.U) ){
         exRego := 0.U //地址1，cmd