修正QSPI/SPI,但没有通过测试,增加包生成工具,尚未完成

src/main/scala/backBoard/shin/Interface.scala

@@ -244,7 +244,8 @@ abstract class InterfaceBase extends Module{
       Seq(
         (addr === "h8".U )  -> cReg.busRate( 7,0 ),
         (addr === "h9".U )  -> cReg.spiSel,
-        (addr === "ha".U & isSlvMode)  -> sReg.localDevIndex,
+        (addr === "ha".U & isSlvMode)  -> sReg.localDevIndex(7,0),
+        (addr === "hb".U & isSlvMode)  -> sReg.localDevIndex(15,8),
 
 
         (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),

src/main/scala/backBoard/shin/SpiInterface.scala

@@ -43,8 +43,10 @@ abstract class SpiInterfaceBase extends Module{
   val isSckPosedge     = ~shiftSCK(2) & shiftSCK(1)
   val isSckPosedgeNext = ShiftRegisters(isSckPosedge, 2, false.B, true.B)
 
+  val isSckNegedge     =  shiftSCK(2) & ~shiftSCK(1)  //确定下降沿放数据到数据线上
 
-  val exReg = Reg(UInt(8.W))
+  val exRego = Reg(UInt(8.W))
+  val exRegi = Reg(UInt(8.W))
 
 
 
@@ -59,12 +61,13 @@ abstract class SpiInterfaceBase extends Module{
 
 
   io.isEnR := 
-             (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & exReg === 1.U & byteSel === 3.U ) |
+             (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & exRegi === 1.U & byteSel === 3.U ) |
              (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead  & byteSel >= 4.U)
   io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
-  io.dataw := exReg
+  io.dataw := exRegi
   io.addrSel :=
     Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
+  val readData = RegEnable(io.datar, io.isEnR)
   
 
   when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -80,9 +83,9 @@ abstract class SpiInterfaceBase extends Module{
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
     addrSel := 0.U
   } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
-    addrSel := exReg
+    addrSel := exRegi
   } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
-    addrSel := Cat(exReg, addrSel(7,0))
+    addrSel := Cat(exRegi, addrSel(7,0))
   } .otherwise{ // byteSel > 1.U
     when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){
       addrSel := addrSel + 1.U
@@ -93,7 +96,7 @@ abstract class SpiInterfaceBase extends Module{
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
     spiCmd  := "hFF".U
   } .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
-    spiCmd := exReg
+    spiCmd := exRegi
   }
 
 
@@ -107,7 +110,7 @@ class SSpiInterface extends SpiInterfaceBase{
   sck     := spi.sck
   csn     := spi.csn
 
-  spi.miso := exReg.extract(7)
+  spi.miso := exRego.extract(7)
 
   when( shiftCSn(2) & ~shiftCSn(1) ){
     bitSel   := 0.U
@@ -117,18 +120,29 @@ class SSpiInterface extends SpiInterfaceBase{
 
   val shiftMOSI = ShiftRegisters(spi.mosi, 3)
 
-  when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳 //第一个byte
+  //输入看SCK上升沿
-    exReg := 0.U
+  when( isSckPosedge & ~shiftCSn(1) ){
-  } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U & (byteSel === 1.U || byteSel === 2.U) ){ //CS为低，且SCK上跳补一拍 的第0bit
+    when( bitSel === 0.U ){
-    exReg := 0.U
+      exRegi := Cat( 0.U, shiftMOSI(1) )
-  } .elsewhen( isSpiWrite ){
+    }.otherwise{
-    exReg := 0.U
+      exRegi := Cat( exRegi(6 ,0), shiftMOSI(1) )
-  } .elsewhen( isSpiRead ){
+    }
-    exReg := io.datar
-  } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
-    exReg := Cat( exReg(6 ,0), shiftMOSI(1) )
   }
 
+  //输出在SCK下降沿准备数据
+  when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
+    exRego := 0.U //第一个byte 地址0
+  } .elsewhen( isSckNegedge & ~shiftCSn(1) ){
+    when( bitSel === 0.U ){
+      when((byteSel === 1.U || byteSel === 2.U) ){
+        exRego := 0.U //地址1，cmd
+      } .elsewhen( isSpiRead ){
+        exRego := io.datar
+      }
+    }.otherwise{
+      exRego := exRego << 1
+    }
+  }
 }
 
 class QSpiInterface extends SpiInterfaceBase{
@@ -136,7 +150,7 @@ class QSpiInterface extends SpiInterfaceBase{
 
   sck       := qspi.sck
   csn       := qspi.csn
-  qspi.miso := exReg(7, 4)
+  qspi.miso := exRego(7, 4)
   qspi.isDirIn := isSpiWrite
 
   when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -147,18 +161,31 @@ class QSpiInterface extends SpiInterfaceBase{
 
   val shiftMOSI = ShiftRegisters(qspi.mosi, 3)
 
-  when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳 //第一个byte
+
-    exReg := 0.U
+
-  } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U & ( byteSel === 1.U || byteSel === 2.U) ){ //CS为低，且SCK上跳补一拍 的第0bit
+  //输入看SCK上升沿
-    exReg := 0.U
+  when( isSckPosedge & ~shiftCSn(1) ){
-  } .elsewhen( io.isEnW ){
+    when( bitSel === 0.U ){
-    exReg := 0.U
+      exRegi := Cat( 0.U, shiftMOSI(1) )
-  } .elsewhen( io.isEnR ){
+    }.otherwise{
-    exReg := io.datar
+      exRegi := Cat( exRegi(3 ,0), shiftMOSI(1) )
-  } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
+    }
-    exReg := Cat( exReg(3,0), shiftMOSI(1) )
   }
 
+  //输出在SCK下降沿准备数据
+  when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
+    exRego := 0.U //第一个byte 地址0
+  } .elsewhen( isSckNegedge & ~shiftCSn(1) ){
+    when( bitSel === 0.U ){
+      when((byteSel === 1.U || byteSel === 2.U) ){
+        exRego := 0.U //地址1，cmd
+      } .elsewhen( isSpiRead ){
+        exRego := readData
+      }
+    }.otherwise{
+      exRego := exRego << 4
+    }
+  }
 
 }
 

tb/shinTest/ShinTopSpiTb.v

@@ -268,12 +268,14 @@ end
 
   reg [7:0] txBuf[0:2047];
   reg [7:0] rxBuf[0:2047];
-  reg [7:0] exChangeReg;
+  reg [7:0] exChangeRego;
+  reg [7:0] exChangeRegi;
 
 
 
-  assign spi_mosi = exChangeReg[7];
+  assign spi_mosi = exChangeRego[7];
-  assign qspi_mosi = exChangeReg[7:4];
+  assign qspi_mosi = exChangeRego[7:4];
+
   wire [3:0] qspi_mux_miso = 
     ( qspi_miso[4*0+3:4*0] & ~{4{spi_csn[ 0]}}) |
     ( qspi_miso[4*1+3:4*1] & ~{4{spi_csn[ 1]}}) |
@@ -313,7 +315,7 @@ always @(posedge clock) begin
     bitCnt  <= #5 ~3'b0;
 
     spi_csn[idx] <= #5 1'b0;
-    exChangeReg <= txBuf[0];
+    exChangeRego <= txBuf[0];
   end
 end
 
@@ -321,6 +323,24 @@ end
 wire isQspi = (idx >= 0 && idx <= 4) || idx >= 10;
 wire [11:0] nextByteCnt = byteCnt + 1;
 
+//输出
+always @(negedge sck) begin
+  if( isBusy ) begin      
+    if( &bitCnt ) begin
+      if( txBuf[2] === 1 & nextByteCnt >= 3) begin
+        exChangeRego <= isQspi ? exChangeRego << 4 : exChangeRego << 1;
+      end else begin
+        exChangeRego <= txBuf[nextByteCnt];
+      end
+    end else begin
+      if( isQspi ) begin
+        exChangeRego <= isQspi ? exChangeRego << 4 : exChangeRego << 1;
+      end
+    end
+  end
+end
+
+//输入
 always @(posedge sck) begin
   if( isBusy ) begin
     if( transCnt <= length ) begin
@@ -333,20 +353,18 @@ always @(posedge sck) begin
       if( &bitCnt ) begin
         byteCnt <= byteCnt +1;
         transCnt <= transCnt + 1;
-        rxBuf[byteCnt] <= isQspi ? {exChangeReg[3:0], qspi_mux_miso} : {exChangeReg[6:0], spi_mux_miso};
+        rxBuf[byteCnt] <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
         if( txBuf[2] === 1 & nextByteCnt >= 4) begin
-          $display("spi read out @ %x", exChangeReg);
+          $display("spi read out %x", exChangeRegi);
         end
         if( txBuf[2] === 1 & nextByteCnt >= 3) begin
-          exChangeReg <= isQspi ? {exChangeReg[3:0], qspi_mux_miso} : {exChangeReg[6:0], spi_mux_miso};
+          exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
         end else begin
-          exChangeReg <= txBuf[nextByteCnt];
+          exChangeRegi <= 0;
         end
       end else begin
         if( isQspi ) begin
-          exChangeReg <= {exChangeReg[3:0], qspi_mux_miso};
+          exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
-        end else begin
-          exChangeReg <= {exChangeReg[6:0], spi_mux_miso};
         end
 
       end
@@ -579,8 +597,11 @@ initial begin
 
 
   //测试
-
+  spi_trans( (16'hc0), (`SPI_READ), (6), (3) );
-  spi_trans( (16'hc0), (`SPI_READ), (6), (3) );//发送SM0 接收SM0, 请求发送
+  spi_trans( (16'h0a), (`SPI_READ), (2), (1) );
+  spi_trans( (16'h0a), (`SPI_READ), (2), (2) );
+  spi_trans( (16'h0a), (`SPI_READ), (2), (3) );
+  spi_trans( (16'h0a), (`SPI_READ), (2), (4) );
 
 
   //读写

tb/shinTest/gen_pkt.py

@@ -0,0 +1,49 @@
+#!/usr/bin/env python
+#encoding=utf-8
+
+from ctypes import *
+
+class TPkt(BigEndianStructure):
+    pass
+TPkt._pack_ = 1
+TPkt._fields_=[
+                ('len',     c_uint, 12),
+                ('rsv1',    c_uint, 2),
+                ('type',    c_uint, 2),
+                ('rsv2',    c_uint16),
+                ('data',    c_uint8 * 2040),
+                ]
+
+class TSubPkt(BigEndianStructure):
+    pass
+
+TSubPkt._pack_ = 1
+TSubPkt._fields_=[
+                ('dev',  c_uint, 14),
+                ('mode', c_uint, 2),
+                ('addr', c_uint16),
+                ('cmd',  c_uint, 4),
+                ('slen', c_uint, 12),
+                ('wkr',  c_uint16)
+                ]
+
+
+
+
+if __name__ == '__main__':
+    packet = b'\0' * 2048
+
+    pkt = cast (packet, POINTER(TPkt)).contents
+    pkt.len = 512
+    pkt.rsv1 = 0
+    pkt.type = 0
+    pkt.rsv2 = 0
+    pkt.data[0] = 1
+    pkt.data[1] = 2
+    pkt.data[2] = 3
+    pkt.data[3] = 4
+
+    for i in range(10):
+        print(hex(packet[i]), ' ')
+
+