diff --git a/src/main/scala/backBoard/ebus/b8b10.scala b/src/main/scala/backBoard/ebus/b8b10.scala
index 9e87ead..1e57fcd 100644
--- a/src/main/scala/backBoard/ebus/b8b10.scala
+++ b/src/main/scala/backBoard/ebus/b8b10.scala
@@ -17,7 +17,9 @@ class Decode_Bundle extends Bundle{
 class b8b10Encode extends Module with RequireAsyncReset{
   val io = IO(new Encode_Bundle)
 
-  val rd = RegInit(false.B)
+  val rdTest = IO(Output(Bool())) //测试使用
+  dontTouch(rdTest)
+  val rd = RegInit(false.B); rdTest := rd
 
 
   val b5b6LookUp = Mux1H(Seq(
diff --git a/src/test/scala/SimCDR.scala b/src/test/scala/SimCDR.scala
index 6a3298c..4f46fec 100644
--- a/src/test/scala/SimCDR.scala
+++ b/src/test/scala/SimCDR.scala
@@ -87,7 +87,7 @@ class SimCDR extends Module with RequireAsyncReset{
 
 
 
-  val isUsing8b10b = true.B
+  val isUsing8b10b = false.B
 
 
   when( isUsing8b10b ){
@@ -106,6 +106,34 @@ class SimCDR extends Module with RequireAsyncReset{
     b8b10Decoder.io.dataIn := 0.U
   }
 
+
+  // val coverData = RegInit(VecInit(Seq.fill(512){false.B}))
+  // when( record.io.enq.fire ){
+  //   for( i <- 0 until 256 ){
+  //     when( record.io.enq.bits === i.U ){
+  //       when( b8b10Encoder.rdTest ){
+  //         coverData(i) := true.B
+  //       } .otherwise{
+  //         coverData(256+i) := true.B
+  //       }
+  //     }
+  //   }
+  // }
+
+  val coverData = RegInit(VecInit(Seq.fill(256){false.B}))
+  when( record.io.enq.fire ){
+    for( i <- 0 until 256 ){
+      when( record.io.enq.bits === i.U ){
+        coverData(i) := true.B
+      }
+    }
+  }
+
+  val coverage = PopCount(coverData.asUInt)
+  when( io.isSuccess ){
+    printf( cf"Coverage: ${coverage}\n")
+  }
+
 }
 
 
diff --git a/tb/shinTest/SimCDRTb.v b/tb/shinTest/SimCDRTb.v
index f86dcbd..dc818d6 100644
--- a/tb/shinTest/SimCDRTb.v
+++ b/tb/shinTest/SimCDRTb.v
@@ -43,8 +43,9 @@ module SimCDRTb(
     wire success;
     wire failed;
 
+    integer seed = 666;
     always @(posedge clock) begin
-        data <= $random;
+        data <= $random(seed);
     end