diff --git a/src/main/scala/backBoard/shin/NSpiInterface.scala b/src/main/scala/backBoard/shin/NSpiInterface.scala
index 7ffa690..eac74bc 100644
--- a/src/main/scala/backBoard/shin/NSpiInterface.scala
+++ b/src/main/scala/backBoard/shin/NSpiInterface.scala
@@ -79,8 +79,8 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
 
   val isAsyncRead = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(false.B)}
 
-  when( bitSel.andR ){ //4线操作
-    when((byteSel === 0.U || byteSel === 1.U || byteSel === 2.U ) ){
+  when( bitSel === 0.U ){ //4线操作
+    when((byteSel === 0.U || byteSel === 1.U || byteSel === 2.U || byteSel === 3.U ) ){
       exRego := 0.U //地址0, 地址1，cmd
     } .elsewhen( isSpiRead ){
       when( ~isAsyncRead ){ //取巧//应该增强约束