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尝试DMA通路，接收好

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This commit is contained in:
RuigeLee
2023-11-09 17:29:33 +08:00
parent 4285882a7a
commit a3cc3d1d3d
4 changed files with 47 additions and 35 deletions
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29
src/main/scala/Switch/DMA.scala
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@@ -17,8 +17,10 @@ abstract class DMAMstBase(val edgeOut: TLEdgeOut)(implicit p: Parameters) extend
class SwitchMuxIO(implicit p: Parameters) extends SwitchBundle{
val dmaMst = new MacTileLinkMasterIO
val sel = Vec( chn, Flipped(new DMA_Register_Bundle) )
val cfg = Vec( chn, Flipped(new DMA_Register_Bundle) )
val selIn = Input(UInt( (log2Ceil(chn)).W))
val selOut = Output(UInt((log2Ceil(chn)).W))
}
@@ -52,7 +54,7 @@ trait DMAMstFSM{ this: DMAMstBase =>
stateNxt :=
Mux1H(Seq(
( stateCur === stateIdle ) -> Mux( (0 until chn).map{i => (io.sel(i).triTx & io.sel(i).r_TxLen > 32.U)}.foldLeft(false.B)(_|_) , stateTx, Mux( rxBuff.mInfo.source.valid, stateRx, stateIdle ) ),
( stateCur === stateIdle ) -> Mux( (0 until chn).map{i => (io.cfg(i).triTx & io.cfg(i).r_TxLen > 32.U)}.foldLeft(false.B)(_|_) , stateTx, Mux( rxBuff.mInfo.source.valid, stateRx, stateIdle ) ),
( stateCur === stateRx ) -> Mux( stateDMA === 0.U, stateIdle, stateRx ),
( stateCur === stateTx ) -> Mux( stateDMA === 0.U, stateIdle, stateTx ),
))
@@ -63,7 +65,7 @@ trait DMAMstFSM{ this: DMAMstBase =>
} .elsewhen( io.dmaMst.A.fire ){
stateDMA := 2.U
} .elsewhen( io.dmaMst.D.fire & isLastD ){
when( stateCur === stateTx & dmaAddress === (io.sel(trigTxNum).r_TxPtr + io.sel(trigTxNum).r_TxLen) ){
when( stateCur === stateTx & dmaAddress === (io.cfg(trigTxNum).r_TxPtr + io.cfg(trigTxNum).r_TxLen) ){
stateDMA := 0.U
} .elsewhen( stateCur === stateRx & ~rxBuff.io.deq.valid ){
stateDMA := 0.U
@@ -82,20 +84,21 @@ trait DMAMstTileLink{ this: DMAMstBase =>
val mInfoValid = stateCur === stateTx
when( rxBuff.mInfo.source.valid & stateCur === stateIdle & stateNxt === stateRx ){
// assert( rxBuff.mInfo.source.bits(48) === 1.U )
trigRxNum := rxBuff.mInfo.source.bits
dmaAddress := io.sel(rxBuff.mInfo.source.bits( log2Ceil(chn)-1, 0 )).r_RxPtr
trigRxNum := io.selIn
dmaAddress := io.cfg(io.selIn).r_RxPtr
}
for( i <- 0 until chn ){
io.sel(i).triRx := rxBuff.io.deq.fire & rxBuff.io.deq.bits.isLast & trigRxNum === i.U
io.sel(i).r_RxLen := RegEnable( rxLength + 1.U, io.sel(i).triRx )
io.cfg(i).triRx := rxBuff.io.deq.fire & rxBuff.io.deq.bits.isLast & trigRxNum === i.U
io.cfg(i).r_RxLen := RegEnable( rxLength + 1.U, io.cfg(i).triRx )
}
for( i <- 0 until chn ){
when( io.sel(i).triTx & io.sel(i).r_TxLen > 32.U & stateCur === stateIdle ){
when( io.cfg(i).triTx & io.cfg(i).r_TxLen > 32.U & stateCur === stateIdle ){
trigTxNum := i.U
dmaAddress := io.sel(i).r_TxPtr
dmaAddress := io.cfg(i).r_TxPtr
assert( stateNxt === stateTx )
}
}
@@ -158,10 +161,10 @@ trait DMAMstBuff{ this: DMAMstBase =>
txBuff.io.enq.valid := io.dmaMst.D.valid & stateCur === stateTx
txBuff.io.enq.bits.data := io.dmaMst.D.bits.data
txBuff.io.enq.bits.isStart := RegEnable( dmaAddress === io.sel(trigTxNum).r_TxPtr, io.dmaMst.A.fire)
txBuff.io.enq.bits.isLast := dmaAddress === (io.sel(trigTxNum).r_TxPtr + io.sel(trigTxNum).r_TxLen)
txBuff.io.enq.bits.isStart := RegEnable( dmaAddress === io.cfg(trigTxNum).r_TxPtr, io.dmaMst.A.fire)
txBuff.io.enq.bits.isLast := dmaAddress === (io.cfg(trigTxNum).r_TxPtr + io.cfg(trigTxNum).r_TxLen)
io.selOut := trigTxNum
}