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尝试DMA通路，接收好

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This commit is contained in:
RuigeLee
2023-11-09 17:29:33 +08:00
parent 4285882a7a
commit a3cc3d1d3d
4 changed files with 47 additions and 35 deletions
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29
src/main/scala/Switch/DMA.scala
View File

@@ -17,8 +17,10 @@ abstract class DMAMstBase(val edgeOut: TLEdgeOut)(implicit p: Parameters) extend
class SwitchMuxIO(implicit p: Parameters) extends SwitchBundle{
val dmaMst = new MacTileLinkMasterIO
val sel = Vec( chn, Flipped(new DMA_Register_Bundle) )
val cfg = Vec( chn, Flipped(new DMA_Register_Bundle) )
val selIn = Input(UInt( (log2Ceil(chn)).W))
val selOut = Output(UInt((log2Ceil(chn)).W))
}
@@ -52,7 +54,7 @@ trait DMAMstFSM{ this: DMAMstBase =>
stateNxt :=
Mux1H(Seq(
( stateCur === stateIdle ) -> Mux( (0 until chn).map{i => (io.sel(i).triTx & io.sel(i).r_TxLen > 32.U)}.foldLeft(false.B)(_|_) , stateTx, Mux( rxBuff.mInfo.source.valid, stateRx, stateIdle ) ),
( stateCur === stateIdle ) -> Mux( (0 until chn).map{i => (io.cfg(i).triTx & io.cfg(i).r_TxLen > 32.U)}.foldLeft(false.B)(_|_) , stateTx, Mux( rxBuff.mInfo.source.valid, stateRx, stateIdle ) ),
( stateCur === stateRx ) -> Mux( stateDMA === 0.U, stateIdle, stateRx ),
( stateCur === stateTx ) -> Mux( stateDMA === 0.U, stateIdle, stateTx ),
))
@@ -63,7 +65,7 @@ trait DMAMstFSM{ this: DMAMstBase =>
} .elsewhen( io.dmaMst.A.fire ){
stateDMA := 2.U
} .elsewhen( io.dmaMst.D.fire & isLastD ){
when( stateCur === stateTx & dmaAddress === (io.sel(trigTxNum).r_TxPtr + io.sel(trigTxNum).r_TxLen) ){
when( stateCur === stateTx & dmaAddress === (io.cfg(trigTxNum).r_TxPtr + io.cfg(trigTxNum).r_TxLen) ){
stateDMA := 0.U
} .elsewhen( stateCur === stateRx & ~rxBuff.io.deq.valid ){
stateDMA := 0.U
@@ -82,20 +84,21 @@ trait DMAMstTileLink{ this: DMAMstBase =>
val mInfoValid = stateCur === stateTx
when( rxBuff.mInfo.source.valid & stateCur === stateIdle & stateNxt === stateRx ){
// assert( rxBuff.mInfo.source.bits(48) === 1.U )
trigRxNum := rxBuff.mInfo.source.bits
dmaAddress := io.sel(rxBuff.mInfo.source.bits( log2Ceil(chn)-1, 0 )).r_RxPtr
trigRxNum := io.selIn
dmaAddress := io.cfg(io.selIn).r_RxPtr
}
for( i <- 0 until chn ){
io.sel(i).triRx := rxBuff.io.deq.fire & rxBuff.io.deq.bits.isLast & trigRxNum === i.U
io.sel(i).r_RxLen := RegEnable( rxLength + 1.U, io.sel(i).triRx )
io.cfg(i).triRx := rxBuff.io.deq.fire & rxBuff.io.deq.bits.isLast & trigRxNum === i.U
io.cfg(i).r_RxLen := RegEnable( rxLength + 1.U, io.cfg(i).triRx )
}
for( i <- 0 until chn ){
when( io.sel(i).triTx & io.sel(i).r_TxLen > 32.U & stateCur === stateIdle ){
when( io.cfg(i).triTx & io.cfg(i).r_TxLen > 32.U & stateCur === stateIdle ){
trigTxNum := i.U
dmaAddress := io.sel(i).r_TxPtr
dmaAddress := io.cfg(i).r_TxPtr
assert( stateNxt === stateTx )
}
}
@@ -158,10 +161,10 @@ trait DMAMstBuff{ this: DMAMstBase =>
txBuff.io.enq.valid := io.dmaMst.D.valid & stateCur === stateTx
txBuff.io.enq.bits.data := io.dmaMst.D.bits.data
txBuff.io.enq.bits.isStart := RegEnable( dmaAddress === io.sel(trigTxNum).r_TxPtr, io.dmaMst.A.fire)
txBuff.io.enq.bits.isLast := dmaAddress === (io.sel(trigTxNum).r_TxPtr + io.sel(trigTxNum).r_TxLen)
txBuff.io.enq.bits.isStart := RegEnable( dmaAddress === io.cfg(trigTxNum).r_TxPtr, io.dmaMst.A.fire)
txBuff.io.enq.bits.isLast := dmaAddress === (io.cfg(trigTxNum).r_TxPtr + io.cfg(trigTxNum).r_TxLen)
io.selOut := trigTxNum
}

14
src/main/scala/Switch/DMARegisters.scala
View File

@@ -24,7 +24,7 @@ class DmaRegIO(implicit p: Parameters) extends SwitchBundle{
val MacAddr = Output(UInt(48.W))
val sel = Vec( chn, new DMA_Register_Bundle )
val cfg = Vec( chn, new DMA_Register_Bundle )
}
class DmaReg(implicit p: Parameters) extends LazyModule with HasSwitchParameters{
@@ -63,12 +63,12 @@ class DmaRegImp(outer: DmaReg)(implicit p: Parameters) extends LazyModuleImp(out
val triRx = for( i <- 0 until chn ) yield { RegInit(false.B) }
for( i <- 0 until chn ) {
io.sel(i).r_TxPtr := txPtr(i)
io.sel(i).r_RxPtr := rxPtr(i)
io.sel(i).r_TxLen := txLen(i)
io.cfg(i).r_TxPtr := txPtr(i)
io.cfg(i).r_RxPtr := rxPtr(i)
io.cfg(i).r_TxLen := txLen(i)
}
for( i <- 0 until chn ) { when( io.sel(i).triRx ) { triRx(i) := true.B } }
for( i <- 0 until chn ) { when( io.cfg(i).triRx ) { triRx(i) := true.B } }
@@ -89,7 +89,7 @@ class DmaRegImp(outer: DmaReg)(implicit p: Parameters) extends LazyModuleImp(out
((0 until chn).map{ i =>
( (10*i + 10) << 2 ) ->
RegFieldGroup("DMATrigger", Some("Tx Control DMA"), Seq(
RegField.w(1, RegWriteFn((valid, data) => { io.sel(i).triTx := (valid & (data === 1.U)) ; true.B} ), RegFieldDesc("bd", s"bd$i", reset=Some(0x0))),
RegField.w(1, RegWriteFn((valid, data) => { io.cfg(i).triTx := (valid & (data === 1.U)) ; true.B} ), RegFieldDesc("bd", s"bd$i", reset=Some(0x0))),
RegField(1, triRx(i), RegFieldDesc("bd", s"bd$i", reset=Some(0x0)))
))
})
@@ -99,7 +99,7 @@ class DmaRegImp(outer: DmaReg)(implicit p: Parameters) extends LazyModuleImp(out
( (10*i + 11) << 2 ) ->
RegFieldGroup("TxRxDMALength", Some("Tx RxControl DMA"), Seq(
RegField(16, txLen(i), RegFieldDesc("txLen", "length of tx", reset=Some(65535))),
RegField.r(16, io.sel(i).r_RxLen, RegFieldDesc("rxLen", "length of rx")),
RegField.r(16, io.cfg(i).r_RxLen, RegFieldDesc("rxLen", "length of rx")),
))
}

33
src/main/scala/Switch/Switch.scala
View File

@@ -60,7 +60,7 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
val dmaMst = Module(new DmaNode(dma_edge))
dmaMst.io.sel <> outer.dmaReg.module.io.sel
dmaMst.io.cfg <> outer.dmaReg.module.io.cfg
dmaMst.io.dmaMst.D.bits := dma_bus.d.bits
@@ -100,6 +100,7 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
val isHit = Reg(Bool())
val destChn = Reg(UInt((log2Ceil(chn+1)).W))
val isMuxBusy = RegInit(false.B)
val dmaSelIn = Reg(UInt((log2Ceil(chn)).W)); dmaMst.io.selIn := dmaSelIn
when( robin.io.deq.rx.fire & robin.io.deq.rx.bits.isLast ){
@@ -108,21 +109,29 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
} .elsewhen( robin.io.deq.mInfo.dest.valid & ~isMuxBusy ){
isMuxBusy := true.B
isHit := false.B
for( i <- 0 until chn+1 ){
when(
robin.io.deq.mInfo.dest.bits === destTable(i)(0) ||
robin.io.deq.mInfo.dest.bits === destTable(i)(1) ||
robin.io.deq.mInfo.dest.bits === destTable(i)(2) ||
robin.io.deq.mInfo.dest.bits === destTable(i)(3)
){
dmaSelIn := robin.io.sel
when( robin.io.sel === (chn+1-1).U ){ //DMA
isHit := true.B
destChn := i.U
}
destChn := dmaMst.io.selOut
} .otherwise{
for( i <- 0 until chn+1 ){
when(
robin.io.deq.mInfo.dest.bits === destTable(i)(0) ||
robin.io.deq.mInfo.dest.bits === destTable(i)(1) ||
robin.io.deq.mInfo.dest.bits === destTable(i)(2) ||
robin.io.deq.mInfo.dest.bits === destTable(i)(3)
){
isHit := true.B
destChn := i.U
}
}
}
}
val tempTxPort = Wire( Vec( chn+1, Decoupled(new Mac_Stream_Bundle) ) )

6
src/main/scala/Switch/SwitchNode.scala
View File

@@ -48,15 +48,15 @@ class MacNode(implicit p: Parameters) extends Mac{
class DmaNode(edgeOut: TLEdgeOut)(implicit p: Parameters) extends DMAMst(edgeOut){
def DmaMac = "habcdef".U(48.W)
// def DmaMac = "habcdef".U(48.W)
ex.tx <> rxBuff.io.enq
txBuff.io.deq <> ex.rx
ex.mInfo.dest.valid := mInfoValid
ex.mInfo.dest.bits := Cat( 1.U, trigTxNum )
ex.mInfo.dest.bits := DontCare
ex.mInfo.source.valid := mInfoValid
ex.mInfo.source.bits := DmaMac
ex.mInfo.source.bits := DontCare
}