From a331599ad49e17b02735b4a33a99a577f9a089fa Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Sun, 8 Oct 2023 15:30:08 +0800
Subject: [PATCH] =?UTF-8?q?bug:=20=E4=BF=A1=E5=8F=B7=E5=90=8C=E6=AD=A5?=
 =?UTF-8?q?=E6=97=B6=E9=92=9F=E5=9F=9F=E9=94=99=E8=AF=AF?=
MIME-Version: 1.0
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---
 src/main/scala/mac/MAC.scala         | 13 +++++++++----
 src/main/scala/mac/MacTilelink.scala | 10 +++++-----
 2 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/src/main/scala/mac/MAC.scala b/src/main/scala/mac/MAC.scala
index 996dc05..0477620 100644
--- a/src/main/scala/mac/MAC.scala
+++ b/src/main/scala/mac/MAC.scala
@@ -239,7 +239,7 @@ val TxStartFrmOut              = Wire(Bool())
 val TxEndFrmOut                = Wire(Bool())
 val ReceivedPauseFrm           = Wire(Bool())
 val ControlFrmAddressOK        = Wire(Bool())
-val RxStatusWriteLatched_sync2 = Wire(Bool())
+val RxStatusWriteLatchedSync   = Wire(Bool())
 val LateCollision              = Wire(Bool())
 val DeferIndication            = Wire(Bool())
 val LateCollLatched            = Wire(Bool())
@@ -305,7 +305,7 @@ dontTouch(TxStartFrmOut              )
 dontTouch(TxEndFrmOut                )
 dontTouch(ReceivedPauseFrm           )
 dontTouch(ControlFrmAddressOK        )
-dontTouch(RxStatusWriteLatched_sync2 )
+dontTouch(RxStatusWriteLatchedSync )
 dontTouch(LateCollision              )
 dontTouch(DeferIndication            )
 dontTouch(LateCollLatched            )
@@ -463,7 +463,7 @@ maccontrol.io.RxFlow                     := r_RxFlow
 maccontrol.io.DlyCrcEn                   := r_DlyCrcEn
 maccontrol.io.TxPauseTV                  := r_TxPauseTV
 maccontrol.io.MAC                        := r_MAC
-maccontrol.io.RxStatusWriteLatched_sync2 := RxStatusWriteLatched_sync2
+maccontrol.io.RxStatusWriteLatched_sync2 := RxStatusWriteLatchedSync
 maccontrol.io.r_PassAll                  := r_PassAll
 
 TxDataOut := maccontrol.io.TxDataOut
@@ -728,7 +728,6 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
   PerPacketPad   := wishbone.io.PerPacketPad
 
   wishbone.io.MRxClk         := io.mrx_clk_pad_i
-  RxStatusWriteLatched_sync2 := wishbone.io.RxStatusWriteLatched_sync2
 
   wishbone.io.r_TxEn     := r_TxEn
   wishbone.io.r_RxEn     := r_RxEn
@@ -894,6 +893,11 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
   val SyncRxStartFrmSync = ShiftRegister(macTileLinkRX.io.LatchedRxStartFrm, 2, false.B, true.B)
   wishbone.io.SyncRxStartFrmSync := SyncRxStartFrmSync
 
+  
+  wishbone.io.RxStatusWriteLatchedSyncb = ShiftRegister(RxStatusWriteLatchedSync, 2, false.B, true.B)
+
+
+
       wishbone.io.LatchedRxLength_rxclk   := macTileLinkRX.io.LatchedRxLength
       wishbone.io.RxStatusInLatched_rxclk := macTileLinkRX.io.RxStatusInLatched
       
@@ -905,6 +909,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
 
 
   withClockAndReset( io.mrx_clk_pad_i.asClock, io.asyncReset ) {
+    RxStatusWriteLatchedSync := ShiftRegister(wishbone.io.RxStatusWriteLatched, 2, false.B, true.B)
     macTileLinkRX.io.ShiftEndedSyncb := ShiftRegister( ShiftEndedSync, 2, false.B, true.B)
     macTileLinkRX.io.RxAbortSyncb    := ShiftRegister( RxAbortSync,    2, false.B, true.B )
     macTileLinkRX.io.Busy_IRQ_syncb  := ShiftRegister( Busy_IRQ_sync,  2, false.B, true.B )
diff --git a/src/main/scala/mac/MacTilelink.scala b/src/main/scala/mac/MacTilelink.scala
index 41d8499..46e24d3 100644
--- a/src/main/scala/mac/MacTilelink.scala
+++ b/src/main/scala/mac/MacTilelink.scala
@@ -60,7 +60,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
 
     // Rx
     val MRxClk     = Input(Bool())         // Receive clock (from PHY)
-    val RxStatusWriteLatched_sync2 = Output(Bool())
 
     //Register
     val r_TxEn    = Input(Bool())          // Transmit enable
@@ -106,6 +105,8 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
 
     val RxReady = Output(Bool())
     val RxStatusIn = Output(UInt(9.W))
+    val RxStatusWriteLatched = Output(Bool())
+    val RxStatusWriteLatchedSyncb = Input(Bool())
   }
 
 
@@ -293,10 +294,9 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
 
 
 
-  val RxStatusWriteLatched = RegInit(false.B)
+  val RxStatusWriteLatched = RegInit(false.B); io.RxStatusWriteLatched := RxStatusWriteLatched
+
 
-  val RxStatusWriteLatched_syncb = ShiftRegister(io.RxStatusWriteLatched_sync2, 2, false.B, true.B)
-  io.RxStatusWriteLatched_sync2    := ShiftRegister(RxStatusWriteLatched, 2, false.B, true.B)
 
 
 
@@ -908,7 +908,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
 
 
   // Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
-  when(RxStatusWriteLatched_syncb){
+  when(io.RxStatusWriteLatchedSyncb){
     RxStatusWriteLatched := false.B
   } .elsewhen(RxStatusWrite){
     RxStatusWriteLatched := true.B