重开ebus项目

2024-09-10 16:12:18 +08:00
parent f7697eed6b
commit a3234d7f48
6 changed files with 0 additions and 0 deletions
--- a/src/main/scala/backBoard/ebus/FSMC.scala.bk
+++ b/src/main/scala/backBoard/ebus/FSMC.scala.bk
@@ -1,42 +0,0 @@
-package BACK
-
-import chisel3._
-import chisel3.util._
-
-
-
-
-
-
-class FSMCSlvIO extends Bundle{
-  val FSMC = new FSMC_Port_Bundle
-
-  val CDRIn  = Flipped(Valid(new CDRData))
-  val CDROut = Valid(new CDRData)
-}
-
-class FSMCSlvBase extends Module{
-  val io: FSMCSlvIO = IO(new FSMCSlvIO)
-
-
-
-
-
-
-
-
-
-
-  mirror.io.datar_b,
-  mirror.io.ce_b,
-  mirror.io.we_b,
-  mirror.io.[10:0] addr_b,
-  mirror.io.[7:0] dataw_b
-}
-
-trait MirrorSRAM { this: FSMCSlvBase =>
-
-
-}
-
-