重开ebus项目

src/main/scala/backBoard/ebus/BackBoardMst.scala.bk

@@ -1,52 +0,0 @@
-package BACK
-
-import chisel3._
-import chisel3.util._
-
-
-class BackBoardMstIO extends Bundle{
-  val downStreamReqDat  = Input( Bool() )
-  val downStreamRespdat = Output(Bool())
-
-  val CS   = Input(Bool())
-  val MISO = Output(Bool())
-  val MOSI = Input(Bool())
-  val SCK  = Input(Bool())
-
-  val interrupt = Output(Bool())
-
-  val clk4            = Input( Bool() )
-
-}
-
-
-class BackBoardMst extends Module{
-  val io: BackBoardMstIO = IO(new BackBoardMstIO)
-
-
-    val spi = Module( new SpiSlv )
-    val in  = Module( new CDR4MultiIn )
-    val out = Module( new CDROutBus )
-
-    spi.io.CS   := io.CS
-    io.MISO     := spi.io.MISO
-    spi.io.MOSI := io.MOSI
-    spi.io.SCK := io.SCK
-
-    // io.interrupt := spi.io.interrupt
-    io.interrupt := false.B
-
-    spi.io.CDRIn  <> in.io.latDat
-    spi.io.CDROut <> out.io.pkgDat
-
-    in.io.clk4 := io.clk4
-    spi.io.clk4 := io.clk4
-
-    in.io.dat  := io.downStreamReqDat
-    io.downStreamRespdat := out.io.dat
-
-
-}
-
-
-