diff --git a/src/main/scala/util/DDFlipFlop.scala b/src/main/scala/util/DDFlipFlop.scala
index 2e3ba49..ebec2d0 100644
--- a/src/main/scala/util/DDFlipFlop.scala
+++ b/src/main/scala/util/DDFlipFlop.scala
@@ -19,8 +19,6 @@ class FDRegInit[T<:Data](init: T, pclk: Clock, nclk: Clock, reset: AsyncReset, m
   if( !mode ){ pReg := next } else { pReg := (nReg.asUInt ^ next.asUInt).asTypeOf(init) }
   nReg := (pReg.asUInt ^ next.asUInt).asTypeOf(init)
 
-  def apply(): T = value
-
 }
 
 object FDRegInit{
@@ -28,6 +26,8 @@ object FDRegInit{
     new FDRegInit(init, pclk, nclk, reset, mode)
   }
 
+  // 隐式转换：FDRegInit[T] → T，读取时自动调用 .apply()
+  implicit def toData[T<:Data](reg: FDRegInit[T]): T = reg.value
 }
 
 
@@ -57,16 +57,19 @@ class FDShiftRegisters[T<:Data]( in: T, n: Int, init: T, en: Bool, pclk: Clock,
   private val nRegs = withClockAndReset(nclk, reset) { RegInit(VecInit(Seq.fill(n)( 0.U.asTypeOf(init)))) }
 
   // 移位逻辑：首位采样输入，其他依次移位
-  if( !mode ){ pRegs(0) := in } else { pRegs(0) := (in.asUInt ^ nRegs(0).asUInt).asTypeOf(init) }
-  for(i <- 1 until n) {
-    if( !mode ){ pRegs(i) := pRegs(i-1) }
-    else { pRegs(i) := (pRegs(i-1).asUInt ^ nRegs(i).asUInt).asTypeOf(init)} 
+  when(en){
+    if( !mode ){ pRegs(0) := in } else { pRegs(0) := (in.asUInt ^ nRegs(0).asUInt).asTypeOf(init) }
+    for(i <- 1 until n) {
+      if( !mode ){ pRegs(i) := pRegs(i-1) }
+      else { pRegs(i) := (pRegs(i-1).asUInt ^ nRegs(i-1).asUInt ^ nRegs(i).asUInt).asTypeOf(init)} 
+    }
+
+    nRegs(0) := (in.asUInt ^ pRegs(0).asUInt).asTypeOf(init)
+    for(i <- 1 until n) {
+      nRegs(i) := (pRegs(i-1).asUInt ^ nRegs(i-1).asUInt ^ pRegs(i).asUInt).asTypeOf(init)
+    }    
   }
 
-  nRegs(0) := (in.asUInt ^ pRegs(0).asUInt).asTypeOf(init)
-  for(i <- 1 until n) {
-    nRegs(i) := (nRegs(i-1).asUInt ^ pRegs(i).asUInt).asTypeOf(init)
-  }
 
   // 输出为 pRegs 与 nRegs 异或
   def apply(): Seq[T] =