diff --git a/Makefile b/Makefile
index 8b0779e..f704475 100644
--- a/Makefile
+++ b/Makefile
@@ -50,7 +50,7 @@ testShin:
 	-I ./generated/shin \
 	-D RANDOMIZE_REG_INIT \
 	./tb/shinTest/ShinTopSpiTb.v 
-	vvp  -N ./tb/build/shinTest.iverilog -lxt2 || true
+	vvp  -N ./tb/build/shinTest.iverilog -lxt2 -fst || true
 	./tb/shinTest/check_testcase.py
 
 testFilter:
@@ -63,6 +63,9 @@ vcdFilter:
 vcdShin:
 	gtkwave ./tb/build/wave.vcd 1>/dev/null 2>&1 &
 
+fstShin:
+	gtkwave ./tb/build/wave.fst 1>/dev/null 2>&1 &
+
 ef: 
 	sbt "test:runMain test.testModule"
 
diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index b1db89b..dccaecc 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -93,7 +93,6 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
   val clearCnt = Reg(UInt(4.W))
   val checkCnt = Reg(UInt(4.W))
-  val arbLock = Reg(UInt( (log2Ceil(8*clkNum)).W ))
   val arbCali = Reg(UInt( (log2Ceil(8*clkNum)).W ))
   val isLock = RegInit(false.B)
 
@@ -149,7 +148,6 @@ trait CDRInMultiSample{ this: CDRInBase =>
     for( i <- 0 until 16 ){
       val j = 50+16 - i - 1
       when( flitReg(j) ^ flitReg(j+1) ){
-        arbLock := j.U
         arbCali := j.U
       }
     }
diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v
index c35813a..57a0243 100644
--- a/tb/shinTest/ShinTopSpiTb.v
+++ b/tb/shinTest/ShinTopSpiTb.v
@@ -460,7 +460,7 @@ initial
 begin
   	spidata_file = $fopen("spi_trans_data.txt", "w");
   	if (!spidata_file) $display("文件打开失败");
-	$dumpfile("./tb/build/wave.vcd"); //生成的vcd文件名称
+	$dumpfile("./tb/build/wave.fst"); //生成的vcd文件名称
 	$dumpvars(0, ShinTopSpiTb);//tb模块名称
 end