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pingpong指针修复

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This commit is contained in:
Ruige Lee
2025-06-25 16:24:21 +08:00
parent 063e446ff9
commit a19dd8ee27
1 changed files with 22 additions and 22 deletions
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44
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -510,10 +510,10 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val downTransLenCnt = RegInit(0.U) val downTransLenCnt = RegInit(0.U)
val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
( ~isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(0).isSeqIndex & downSubMsgHeadInfo(0).devIndex === localDevIndex) || ( downSubMsgHeadInfo(0).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | ( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(0).isSeqIndex & downSubMsgHeadInfo(0).devIndex === localDevIndex) || ( downSubMsgHeadInfo(0).isLgcIndex & downTransLenCnt =/= 0.U) ) ) |
( isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(1).isSeqIndex & downSubMsgHeadInfo(1).devIndex === localDevIndex) || ( downSubMsgHeadInfo(1).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | ( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(1).isSeqIndex & downSubMsgHeadInfo(1).devIndex === localDevIndex) || ( downSubMsgHeadInfo(1).isLgcIndex & downTransLenCnt =/= 0.U) ) ) |
( ~isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) | ( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) |
( isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
) )
@@ -554,8 +554,8 @@ trait SlaveParserRW{ this: SlaveParserBase =>
)){//组合逻辑 )){//组合逻辑
logicAddrwNext := Cat( downRecParser.io.subMsgHeadReq.bits.devIndex, downRecParser.io.subMsgHeadReq.bits.address ) logicAddrwNext := Cat( downRecParser.io.subMsgHeadReq.bits.devIndex, downRecParser.io.subMsgHeadReq.bits.address )
} .elsewhen( downRecParser.io.data.fire & ( } .elsewhen( downRecParser.io.data.fire & (
( ~isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) | ( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) |
( isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex ) ( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex )
)){//组合逻辑 )){//组合逻辑
logicAddrwNext := logicAddrw + 1.U logicAddrwNext := logicAddrw + 1.U
} .otherwise{//组合逻辑 } .otherwise{//组合逻辑
@@ -663,8 +663,8 @@ trait SlaveParserRW{ this: SlaveParserBase =>
when( isUpLgcAddrrAcquireTrans & ( when( isUpLgcAddrrAcquireTrans & (
(upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) | (upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) |
(~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) |
( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex ))
)){ //装填计数器 )){ //装填计数器
upTransLenCnt := acquireUpTransLen upTransLenCnt := acquireUpTransLen
} .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U ){ } .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U ){
@@ -684,8 +684,8 @@ trait SlaveParserRW{ this: SlaveParserBase =>
logicAddrrNext := Cat( upRecParser.io.subMsgHeadReq.bits.devIndex, upRecParser.io.subMsgHeadReq.bits.address ) logicAddrrNext := Cat( upRecParser.io.subMsgHeadReq.bits.devIndex, upRecParser.io.subMsgHeadReq.bits.address )
} .elsewhen( upRecParser.io.data.fire){ } .elsewhen( upRecParser.io.data.fire){
when( when(
(~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(0).isLgcIndex ) | ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(0).isLgcIndex ) |
( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(1).isLgcIndex ) (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(1).isLgcIndex )
){//组合逻辑 ){//组合逻辑
logicAddrrNext := logicAddrr + 1.U logicAddrrNext := logicAddrr + 1.U
} .otherwise{ } .otherwise{
@@ -704,17 +704,17 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val isSeqRead = val isSeqRead =
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
(~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) )) | ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) )) |
( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) )) | (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) )) |
(~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) | ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) |
( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) )
) )
) & ( (RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire ) ) & ( (RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire )
val isLgcRead = val isLgcRead =
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
(~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) | ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) |
( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) )) (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) ))
) )
) & ( RegNext(isUpLgcAddrrAcquireTrans) | upRecParser.io.data.fire ) ) & ( RegNext(isUpLgcAddrrAcquireTrans) | upRecParser.io.data.fire )
@@ -734,14 +734,14 @@ trait SlaveParserRW{ this: SlaveParserBase =>
} .elsewhen( isUpLgcAddrrAcquireTrans ){ } .elsewhen( isUpLgcAddrrAcquireTrans ){
when( when(
(upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) | (upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) |
(~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) |
( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex ))
){ ){
addrr := acquireUpPhyAddrr addrr := acquireUpPhyAddrr
} }
} .elsewhen( isLvdsEnR & ( } .elsewhen( isLvdsEnR & (
(~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) |
( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex ))
)){ )){
assert(~isUpLgcAddrrAcquireTrans) assert(~isUpLgcAddrrAcquireTrans)
addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U ) addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U )
@@ -900,8 +900,8 @@ trait SlaveParserSync{ this: SlaveParserBase =>
//下行接收 //下行接收
val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
( ~isDownRecPing & downSubMsgHeadInfo(0).devIndex === 0.U & downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) | ( isDownRecPing & downSubMsgHeadInfo(0).devIndex === 0.U & downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) |
( isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC ) ( ~isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC )
) )
val syncCnt = Reg(UInt(4.W)) val syncCnt = Reg(UInt(4.W))