diff --git a/src/main/scala/backBoard/shin/MasterParser.scala b/src/main/scala/backBoard/shin/MasterParser.scala
index b80ac36..88289c6 100644
--- a/src/main/scala/backBoard/shin/MasterParser.scala
+++ b/src/main/scala/backBoard/shin/MasterParser.scala
@@ -114,14 +114,14 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
   io.downOut.bits.tdata := Mux1H(Seq(
     ( txCnt  <  txLen       ) -> 
       MuxCase( io.sram_r.datar, Array(
-        ( isRplTimeStamp  & ( txCnt === rplCnt0  ) ) -> io.cReg.timeStamp(7,0),
-        ( isRplTimeStamp  & ( txCnt === rplCnt1  ) ) -> RegEnable(io.cReg.timeStamp(15,8),  io.downOut.fire & txCnt === rplCnt0 ),
-        ( isRplTimeStamp  & ( txCnt === rplCnt2  ) ) -> RegEnable(io.cReg.timeStamp(23,16), io.downOut.fire & txCnt === rplCnt0 ),
-        ( isRplTimeStamp  & ( txCnt === rplCnt3  ) ) -> RegEnable(io.cReg.timeStamp(31,24), io.downOut.fire & txCnt === rplCnt0 ),
-        ( isRplTimeStamp  & ( txCnt === rplCnt4  ) ) -> RegEnable(io.cReg.timeStamp(39,32), io.downOut.fire & txCnt === rplCnt0 ),
-        ( isRplTimeStamp  & ( txCnt === rplCnt5  ) ) -> RegEnable(io.cReg.timeStamp(47,40), io.downOut.fire & txCnt === rplCnt0 ),
-        ( isRplTimeStamp  & ( txCnt === rplCnt6  ) ) -> RegEnable(io.cReg.timeStamp(55,48), io.downOut.fire & txCnt === rplCnt0 ),
-        ( isRplTimeStamp  & ( txCnt === rplCnt7  ) ) -> RegEnable(io.cReg.timeStamp(63,56), io.downOut.fire & txCnt === rplCnt0 ),
+        ( isRplTimeStamp  & ( txCnt === rplCnt0  ) ) -> RegEnable(io.cReg.timeStamp(7,0),   io.req ),
+        ( isRplTimeStamp  & ( txCnt === rplCnt1  ) ) -> RegEnable(io.cReg.timeStamp(15,8),  io.req ),
+        ( isRplTimeStamp  & ( txCnt === rplCnt2  ) ) -> RegEnable(io.cReg.timeStamp(23,16), io.req ),
+        ( isRplTimeStamp  & ( txCnt === rplCnt3  ) ) -> RegEnable(io.cReg.timeStamp(31,24), io.req ),
+        ( isRplTimeStamp  & ( txCnt === rplCnt4  ) ) -> RegEnable(io.cReg.timeStamp(39,32), io.req ),
+        ( isRplTimeStamp  & ( txCnt === rplCnt5  ) ) -> RegEnable(io.cReg.timeStamp(47,40), io.req ),
+        ( isRplTimeStamp  & ( txCnt === rplCnt6  ) ) -> RegEnable(io.cReg.timeStamp(55,48), io.req ),
+        ( isRplTimeStamp  & ( txCnt === rplCnt7  ) ) -> RegEnable(io.cReg.timeStamp(63,56), io.req ),
         ( isRplDeltaStamp & ( txCnt === rplCnt8  ) ) -> io.cReg.mstDeltaTime(7,0),
         ( isRplDeltaStamp & ( txCnt === rplCnt9  ) ) -> io.cReg.mstDeltaTime(15,8),
         ( isRplDeltaStamp & ( txCnt === rplCnt10 ) ) -> io.cReg.mstDeltaTime(23,16),