over sample in spi

src/main/scala/backBoard/BackBoardMst.scala

@@ -17,14 +17,13 @@ class BackBoardMstIO extends Bundle{
 
   val clk4            = Input( Bool() )
 
-  val reset = Input(Bool())
 }
 
 
-class BackBoardMst extends RawModule{
+class BackBoardMst extends Module{
   val io: BackBoardMstIO = IO(new BackBoardMstIO)
 
-  withClockAndReset( io.SCK.asClock, io.reset.asAsyncReset ){
+
     val spi = Module( new SpiSlv )
     val in  = Module( new CDR4MultiIn )
     val out = Module( new CDROutBus )
@@ -32,25 +31,21 @@ class BackBoardMst extends RawModule{
     spi.io.CS   := io.CS
     io.MISO     := spi.io.MISO
     spi.io.MOSI := io.MOSI
+    spi.io.SCK := io.SCK
 
-    io.interrupt := spi.io.interrupt
+    // io.interrupt := spi.io.interrupt
+    io.interrupt := false.B
 
     spi.io.CDRIn  <> in.io.latDat
     spi.io.CDROut <> out.io.pkgDat
 
     in.io.clk4 := io.clk4
+    spi.io.clk4 := io.clk4
 
     in.io.dat  := io.downStreamReqDat
     io.downStreamRespdat := out.io.dat
 
-    spi.clock := io.SCK.asClock
-    in.clock  := io.SCK.asClock
-    out.clock := io.SCK.asClock
 
-    spi.reset := io.reset.asAsyncReset
-    in.reset  := io.reset.asAsyncReset
-    out.reset := io.reset.asAsyncReset
-  }
 }