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更新慢速qspi

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RuigeLee
2025-09-19 14:26:54 +08:00
parent fc8d43a4a3
commit 9fdd360854
1 changed files with 4 additions and 9 deletions
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13
src/main/scala/backBoard/shin/SpiInterface.scala
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@@ -163,15 +163,10 @@ class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
qspi.isDirIn := ~isSpiRead qspi.isDirIn := ~isSpiRead
io.isEnR := io.isEnR :=
(
if(edge){
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & shiftMOSI(1) === "b1000".U & byteSel === 2.U ) | (isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & shiftMOSI(1) === "b1000".U & byteSel === 2.U ) |
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U) (isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U)
} else {
(isSckNegedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 2.U)
}
)
@@ -203,8 +198,8 @@ class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
(if( edge ) {isSckPosedge} else {isSckNegedge}) (if( edge ) {isSckPosedge} else {isSckNegedge})
& ~shiftCSn(1) & ~shiftCSn(1)
){ ){
when( bitSel.andR ){ when( (if( edge ) { bitSel.andR } else { bitSel === 0.U }) ){
when((byteSel === 0.U || byteSel === 1.U) ){ when((byteSel === 0.U || byteSel === 1.U || byteSel === 2.U) ){
exRego := 0.U //地址1，cmd exRego := 0.U //地址1，cmd
} .elsewhen( isSpiRead ){ } .elsewhen( isSpiRead ){
exRego := io.datar exRego := io.datar