多相位时钟可以使用

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -58,7 +58,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
   val clkNum: Int = 8
   require(clkNum >= 4)
 
-  //multiCLK 需要按照超前相位接线，即0为最后到达，1次后
+  //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
   val multiCLK = IO(Input(Vec(clkNum, Bool())))
 
   // val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
@@ -68,17 +68,31 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
   // val arbCnt  = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
   // arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) )
-  val arbCnt = RegInit("b1".U(clkNum.W))
-  arbCnt := Cat( arbCnt(clkNum-2,0), arbCnt.extract(clkNum-1) )
 
   // val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
   // when( sampleReg(0) ^ sampleReg(1) ){
   //   arbLock := arbCnt
   // }
   val arbLock = Reg(UInt( clkNum.W ))
+
+  //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
   when( sampleReg(0) ^ sampleReg(1) ){
-    arbLock := arbCnt
+    arbLock := "b1".U(clkNum.W) << 2
-  }
+  } .elsewhen( sampleReg(1) ^ sampleReg(2) ){
+    arbLock := "b1".U(clkNum.W) << 3
+  } .elsewhen( sampleReg(2) ^ sampleReg(3) ){
+    arbLock := "b1".U(clkNum.W) << 4
+  } .elsewhen( sampleReg(3) ^ sampleReg(4) ){
+    arbLock := "b1".U(clkNum.W) << 5
+  } .elsewhen( sampleReg(4) ^ sampleReg(5) ){
+    arbLock := "b1".U(clkNum.W) << 6
+  } .elsewhen( sampleReg(5) ^ sampleReg(6) ){
+    arbLock := "b1".U(clkNum.W) << 7
+  } .elsewhen( sampleReg(6) ^ sampleReg(7) ){
+    arbLock := "b1".U(clkNum.W) << 0
+  } .elsewhen( sampleReg(7) ^ sampleReg(0) ){
+    arbLock := "b1".U(clkNum.W) << 1
+  } 
 
 
   // val asyncSerDat = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegNext(
@@ -94,7 +108,8 @@ trait CDRInMultiSample{ this: CDRInBase =>
     Mux1H(
       (for { i <- 0 until clkNum; j <- 0 until clkNum } yield {
         //跳变沿到来锁定的位置        锁定拍当前所在的位置          选择锁定拍后一拍的值认为是正确值
-        ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> sampleReg((clkNum - 1 - i + j) % clkNum)
+        // ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> sampleReg((clkNum - 1 - i + j) % clkNum)
+        (arbLock === (1.U << i))                                -> sampleReg(i)
       })
     )
 

tb/shinTest/ShinTopSpiTb.v

@@ -338,7 +338,7 @@ generate
   for( genvar i = 0; i < 8; i = i + 1 ) begin
     initial begin
       multiCLK[i] = 0;
-      for( integer j = i; j < 8; j = j + 1 ) begin
+      for( integer j = 0; j < i; j = j + 1 ) begin
         #20
         ;
       end