diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index fb034aa..662e1cb 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -3,6 +3,19 @@ package BACK
 import chisel3._
 import chisel3.util._
 
+
+class EBMMU_Bundle extends Bundle{
+  val lAddr = UInt(30.W)
+  val pAddr = UInt(16.W)
+  val length = UInt(16.W)
+  val op = UInt(8.W)
+  val isEnable = Bool()
+
+  def EBMMU_OP_RD = op === 1.U
+  def EBMMU_OP_WR = op === 2.U
+  def EBMMU_OP_RW = op === 3.U
+}
+
 class CommonRegisterBundle extends Bundle{
   val mstOrSlv  = UInt(2.W)
   def modeSel:Bool = mstOrSlv === "h1".U
@@ -72,13 +85,7 @@ class SlaveRegisterBundle extends Bundle{
   // val nodeSetAddr = UInt(16.W)
 
 
-  // val ebmmu = Vec(8, new Bundle{
-  //   val logicAddr = UInt(32.W)
-  //   val length = UInt(16.W)
-  //   val phyAddr = UInt(32.W)
-  //   val op = UInt(2.W)
-  //   val enable = Bool()
-  // })
+  val ebmmu = Vec(8, new EBMMU_Bundle)
 
   // val intStatus = UInt(16.W)
   // val mb = Vec(8, new Bundle{
@@ -364,6 +371,21 @@ abstract class InterfaceBase extends Module{
       ( 0 until 128 ).map{ i =>
         ( addr === ("h180".U(16.W) + i.U )   ) -> cReg.custom(i)
       } ++
+      ( 0 until 8 ).map{ i =>
+        ( ( addr === ( "h200".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr( 7, 0),
+        ( ( addr === ( "h201".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(15, 8),
+        ( ( addr === ( "h202".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(23,16),
+        ( ( addr === ( "h203".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(29,24),
+
+        ( ( addr === ( "h204".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).pAddr( 7, 0),
+        ( ( addr === ( "h205".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).pAddr(15, 8),
+
+        ( ( addr === ( "h206".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).length( 7, 0),
+        ( ( addr === ( "h207".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).length(15, 8),
+
+        ( ( addr === ( "h208".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).op,
+        ( ( addr === ( "h209".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).isEnable,
+      } ++
       ( 0 until 8 ).map{ i =>
         ( addr === ("h302".U(16.W) + (i*4).U) )  -> cReg.smTrigLen(i)(7,0)
       } ++
@@ -725,6 +747,33 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
       }      
     }
   }
+
+
+  ( 0 until 8 ).map{ i =>
+    sReg.ebmmu(i).lAddr := Cat(
+      RegEnable( io.lvds.dataw(5,0), 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
+      RegEnable( io.lvds.dataw,      0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ),
+      RegEnable( io.lvds.dataw,      0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ),
+      RegEnable( io.lvds.dataw,      0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ),
+    )
+
+    sReg.ebmmu(i).pAddr := Cat(
+      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ),
+      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ),
+    )
+
+    sReg.ebmmu(i).length := Cat(
+      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ),
+      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ),
+    )
+
+    sReg.ebmmu(i).op :=
+      RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )
+
+    sReg.ebmmu(i).isEnable :=
+      RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) )
+  }
+
 }
 
 trait InterfaceSync{ this: InterfaceBase =>