macregister
This commit is contained in:
RuigeLee
@@ -3,4 +3,438 @@ package MAC
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import chisel3._
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import chisel3.util._
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class MacRegIO extends Bundle{
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val DataIn = Input(UInt(32.W))
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val Address = Input(UInt(8.W))
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val Rw = Input(Bool())
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val Cs = Input(UInt(4.W))
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val WCtrlDataStart = Input(Bool())
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val RStatStart = Input(Bool())
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val UpdateMIIRX_DATAReg = Input(Bool())
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val Prsd = Input(UInt(16.W))
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val NValid_stat = Input(Bool())
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val Busy_stat = Input(Bool())
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val LinkFail = Input(Bool())
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val TxB_IRQ = Input(Bool())
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val TxE_IRQ = Input(Bool())
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val RxB_IRQ = Input(Bool())
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val RxE_IRQ = Input(Bool())
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val Busy_IRQ = Input(Bool())
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val RstTxPauseRq = Input(Bool())
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val TxCtrlEndFrm = Input(Bool())
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val StartTxDone = Input(Bool())
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val TxClk = Input(Bool())
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val RxClk = Input(Bool())
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val SetPauseTimer = Input(Bool())
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val dbg_dat = Input(UInt(32.W)) // debug data input
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val DataOut = Output(UInt(32.W))
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val r_RecSmall = Output(Bool())
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val r_Pad = Output(Bool())
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val r_HugEn = Output(Bool())
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val r_CrcEn = Output(Bool())
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val r_DlyCrcEn = Output(Bool())
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val r_FullD = Output(Bool())
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val r_ExDfrEn = Output(Bool())
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val r_NoBckof = Output(Bool())
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val r_LoopBck = Output(Bool())
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val r_IFG = Output(Bool())
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val r_Pro = Output(Bool())
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val r_Iam = Output(Bool())
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val r_Bro = Output(Bool())
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val r_NoPre = Output(Bool())
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val r_TxEn = Output(Bool())
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val r_RxEn = Output(Bool())
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val r_HASH0 = Output(UInt(32.W))
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val r_HASH1 = Output(UInt(32.W))
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val r_IPGT = Output(UInt(7.W))
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val r_IPGR1 = Output(UInt(7.W))
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val r_IPGR2 = Output(UInt(7.W))
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val r_MinFL = Output(UInt(16.W))
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val r_MaxFL = Output(UInt(16.W))
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val r_MaxRet = Output(UInt(4.W))
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val r_CollValid = Output(UInt(6.W))
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val r_TxFlow = Output(Bool())
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val r_RxFlow = Output(Bool())
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val r_PassAll = Output(Bool())
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val r_MiiNoPre = Output(Bool())
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val r_ClkDiv = Output(UInt(8.W))
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val r_WCtrlData = Output(Bool())
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val r_RStat = Output(Bool())
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val r_ScanStat = Output(Bool())
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val r_RGAD = Output(UInt(5.W))
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val r_FIAD = Output(UInt(5.W))
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val r_CtrlData = Output(UInt(16.W))
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val r_MAC = Output(UInt(48.W))
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val r_TxBDNum = Output(UInt(8.W))
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val int_o = Output(Bool())
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val r_TxPauseTV = Output(UInt(16.W))
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val r_TxPauseRq = Output(Bool())
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}
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class MacReg extends Module{
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val io: MacRegIO = IO(new MacRegIO)
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val Write = io.Cs & Fill(4, io.Rw)
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val Read = io.Cs.orR & ~io.Rw
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val MODER_Sel = ( io.Address === "h0".U )
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val INT_SOURCE_Sel = ( io.Address === "h1".U )
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val INT_MASK_Sel = ( io.Address === "h2".U )
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val IPGT_Sel = ( io.Address === "h3".U )
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val IPGR1_Sel = ( io.Address === "h4".U )
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val IPGR2_Sel = ( io.Address === "h5".U )
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val PACKETLEN_Sel = ( io.Address === "h6".U )
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val COLLCONF_Sel = ( io.Address === "h7".U )
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val CTRLMODER_Sel = ( io.Address === "h9".U )
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val MIIMODER_Sel = ( io.Address === "hA".U )
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val MIICOMMAND_Sel = ( io.Address === "hB".U )
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val MIIADDRESS_Sel = ( io.Address === "hC".U )
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val MIITX_DATA_Sel = ( io.Address === "hD".U )
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val MAC_ADDR0_Sel = ( io.Address === "h10".U )
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val MAC_ADDR1_Sel = ( io.Address === "h11".U )
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val HASH0_Sel = ( io.Address === "h12".U )
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val HASH1_Sel = ( io.Address === "h13".U )
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val TXCTRL_Sel = ( io.Address === "h14".U )
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val RXCTRL_Sel = ( io.Address === "h15".U )
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val DBG_REG_Sel = ( io.Address === "h16".U )
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val TX_BD_NUM_Sel = ( io.Address === "h8".U )
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val MODER_Wr = Write(2,0) & Fill(3, MODER_Sel)
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val INT_SOURCE_Wr = Write.extract(0) & INT_SOURCE_Sel
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val INT_MASK_Wr = Write.extract(0) & INT_MASK_Sel
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val IPGT_Wr = Write.extract(0) & IPGT_Sel
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val IPGR1_Wr = Write.extract(0) & IPGR1_Sel
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val IPGR2_Wr = Write.extract(0) & IPGR2_Sel
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val PACKETLEN_Wr = Write & Fill(4, PACKETLEN_Sel)
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val COLLCONF_Wr = Cat( Write.extract(2) & COLLCONF_Sel, 0.U(1.W), Write.extract(0) & COLLCONF_Sel)
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val CTRLMODER_Wr = Write.extract(0) & CTRLMODER_Sel
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val MIIMODER_Wr = Write(1,0) & Fill(2, MIIMODER_Sel)
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val MIICOMMAND_Wr = Write.extract(0) & MIICOMMAND_Sel;
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val MIIADDRESS_Wr = Write(1,0) & Fill(2, MIIADDRESS_Sel)
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val MIITX_DATA_Wr = Write(1,0) & Fill(2, MIITX_DATA_Sel)
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val MIIRX_DATA_Wr = io.UpdateMIIRX_DATAReg
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val MAC_ADDR0_Wr = Write & Fill(4, MAC_ADDR0_Sel)
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val MAC_ADDR1_Wr = Write(1,0) & Fill(2, MAC_ADDR1_Sel)
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val HASH0_Wr = Write & Fill(4, HASH0_Sel)
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val HASH1_Wr = Write & Fill(4, HASH1_Sel)
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val TXCTRL_Wr = Write(2,0) & Fill(3, TXCTRL_Sel)
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val TX_BD_NUM_Wr = Write.extract(0) & TX_BD_NUM_Sel & (io.DataIn <= "h80".U)
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val INT_SOURCEOut = Wire(UInt(32.W))
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val MIISTATUSOut = Cat( io.NValid_stat, io.Busy_stat, io.LinkFail )
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val MODEROut = Cat( // MODER Register
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RegEnable( io.DataIn.extract(16), 0.U(1.W), MODER_Wr.extract(2) ),
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RegEnable( io.DataIn(15,8), "hA0".U(8.W), MODER_Wr.extract(1) ),
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RegEnable( io.DataIn( 7,0), 0.U(8.W), MODER_Wr.extract(0) ),
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)
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val INT_MASKOut = RegEnable(io.DataIn(6,0), 0.U(7.W), INT_MASK_Wr) // INT_MASK Register
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val IPGTOut = RegEnable(io.DataIn(6,0), "h12".U(7.W), IPGT_Wr ) // IPGT Register
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val IPGR1Out = RegEnable(io.DataIn(6,0), "h0C".U(7.W), IPGR1_Wr) // IPGR1 Register
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val IPGR2Out = RegEnable(io.DataIn(6,0), "h12".U(7.W), IPGR2_Wr)
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val PACKETLENOut = Cat( // PACKETLEN Register
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RegEnable(io.DataIn(31,24), 0.U(8.W), PACKETLEN_Wr.extract(3)),
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RegEnable(io.DataIn(23,16), "h40".U(8.W), PACKETLEN_Wr.extract(2)),
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RegEnable(io.DataIn(15,8 ), 6.U(8.W), PACKETLEN_Wr.extract(1)),
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RegEnable(io.DataIn( 7,0 ), 0.U(8.W), PACKETLEN_Wr.extract(0))
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)
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val COLLCONFOut = Cat( // COLLCONF Register
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RegEnable(io.DataIn(19,16), "hF".U(4.W), COLLCONF_Wr.extract(2)),
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0.U(10.W),
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RegEnable(io.DataIn(5,0), "h3f".U(6.W), COLLCONF_Wr.extract(0))
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)
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val TX_BD_NUMOut = RegEnable(io.DataIn(7,0), "h40".U(8.W), TX_BD_NUM_Wr) // TX_BD_NUM Register
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val CTRLMODEROut = RegEnable(io.DataIn(2,0), 0.U(3.W), CTRLMODER_Wr.extract(0)) // CTRLMODER Register
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val MIIMODEROut = Cat( // MIIMODER Register
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RegEnable(io.DataIn.extract(8), 0.U(1.W), MIIMODER_Wr.extract(1)),
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RegEnable(io.DataIn(7,0), "h64".U(8.W), MIIMODER_Wr.extract(0))
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)
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val MIICOMMANDOut0 = RegEnable(io.DataIn.extract(0), 0.U(1.W), MIICOMMAND_Wr)
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val MIICOMMANDOut1 = RegInit(false.B)
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val MIICOMMANDOut2 = RegInit(false.B)
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when(io.RStatStart){
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MIICOMMANDOut1 := false.B
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} .elsewhen(MIICOMMAND_Wr){
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MIICOMMANDOut1 := io.DataIn.extract(1)
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}
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when(io.WCtrlDataStart){
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MIICOMMANDOut2 := false.B
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} .elsewhen(MIICOMMAND_Wr){
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MIICOMMANDOut2 := io.DataIn.extract(2)
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}
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val MIICOMMANDOut = Cat(MIICOMMANDOut2, MIICOMMANDOut1, MIICOMMANDOut0) // MIICOMMAND Register
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val MIIADDRESSOut = Cat( // MIIADDRESSRegister
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RegEnable(io.DataIn(12,8), 0.U(5.W), MIIADDRESS_Wr.extract(1)),
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0.U(3.W),
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RegEnable(io.DataIn( 4,0), 0.U(5.W), MIIADDRESS_Wr.extract(0))
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)
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val MIITX_DATAOut = Cat( // MIITX_DATA Register
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RegEnable(io.DataIn(15,8), 0.U(8.W), MIITX_DATA_Wr.extract(1)),
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RegEnable(io.DataIn( 7,0), 0.U(8.W), MIITX_DATA_Wr.extract(0))
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)
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val MIIRX_DATAOut = RegEnable(io.Prsd, 0.U(16.W), MIIRX_DATA_Wr) // MIIRX_DATA Register
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val MAC_ADDR0Out = Cat( // MAC_ADDR0 Register
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RegEnable(io.DataIn(31,24), 0.U(8.W), MAC_ADDR0_Wr.extract(3)),
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RegEnable(io.DataIn(23,16), 0.U(8.W), MAC_ADDR0_Wr.extract(2)),
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RegEnable(io.DataIn(15, 8), 0.U(8.W), MAC_ADDR0_Wr.extract(1)),
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RegEnable(io.DataIn(7 , 0), 0.U(8.W), MAC_ADDR0_Wr.extract(0))
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)
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val MAC_ADDR1Out = Cat( // MAC_ADDR1 Register
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RegEnable(io.DataIn(15,8), 0.U(8.W), MAC_ADDR1_Wr.extract(1)),
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RegEnable(io.DataIn(7 ,0), 0.U(8.W), MAC_ADDR1_Wr.extract(0))
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)
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val HASH0Out = Cat( // RXHASH0 Register
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RegEnable(io.DataIn(31,24), 0.U(8.W), HASH0_Wr.extract(3)),
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RegEnable(io.DataIn(23,16), 0.U(8.W), HASH0_Wr.extract(2)),
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RegEnable(io.DataIn(15, 8), 0.U(8.W), HASH0_Wr.extract(1)),
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RegEnable(io.DataIn(7 , 0), 0.U(8.W), HASH0_Wr.extract(0))
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)
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val HASH1Out = Cat( // RXHASH1 Register
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RegEnable(io.DataIn(31,24), 0.U(8.W), HASH1_Wr.extract(3)),
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RegEnable(io.DataIn(23,16), 0.U(8.W), HASH1_Wr.extract(2)),
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RegEnable(io.DataIn(15, 8), 0.U(8.W), HASH1_Wr.extract(1)),
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RegEnable(io.DataIn(7 , 0), 0.U(8.W), HASH1_Wr.extract(0))
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)
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val TXCTRLOut16 = RegInit(false.B)
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when( io.RstTxPauseRq ){
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TXCTRLOut16 := false.B
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} .elsewhen( TXCTRL_Wr.extract(2) ){
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TXCTRLOut16 := io.DataIn.extract(16)
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}
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val TXCTRLOut = Cat( // TXCTRL Register
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TXCTRLOut16,
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RegEnable(io.DataIn(15,8), 0.U(8.W), TXCTRL_Wr.extract(1)),
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RegEnable(io.DataIn(7, 0), 0.U(8.W), TXCTRL_Wr.extract(0))
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)
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// Reading data from registers
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io.DataOut :=
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Mux(
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Read,
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Mux1H(Seq(
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(io.Address === 0.U ) -> MODEROut,
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(io.Address === 1.U ) -> INT_SOURCEOut,
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(io.Address === 2.U ) -> INT_MASKOut,
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(io.Address === 3.U ) -> IPGTOut,
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(io.Address === 4.U ) -> IPGR1Out,
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(io.Address === 5.U ) -> IPGR2Out,
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(io.Address === 6.U ) -> PACKETLENOut,
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(io.Address === 7.U ) -> COLLCONFOut,
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(io.Address === 9.U ) -> CTRLMODEROut,
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(io.Address === 10.U ) -> MIIMODEROut,
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(io.Address === 11.U ) -> MIICOMMANDOut,
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(io.Address === 12.U ) -> MIIADDRESSOut,
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(io.Address === 13.U ) -> MIITX_DATAOut,
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(io.Address === 14.U ) -> MIIRX_DATAOut,
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(io.Address === 15.U ) -> MIISTATUSOut,
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(io.Address === 16.U ) -> MAC_ADDR0Out,
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(io.Address === 17.U ) -> MAC_ADDR1Out,
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(io.Address === 8.U ) -> TX_BD_NUMOut,
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(io.Address === 18.U ) -> HASH0Out,
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(io.Address === 19.U ) -> HASH1Out,
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(io.Address === 20.U ) -> TXCTRLOut,
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(io.Address === 22.U ) -> io.dbg_dat,
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)),
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0.U
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)
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io.r_RecSmall := MODEROut.extract(16)
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io.r_Pad := MODEROut.extract(15)
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io.r_HugEn := MODEROut.extract(14)
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io.r_CrcEn := MODEROut.extract(13)
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io.r_DlyCrcEn := MODEROut.extract(12)
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io.r_FullD := MODEROut.extract(10)
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io.r_ExDfrEn := MODEROut.extract( 9)
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io.r_NoBckof := MODEROut.extract( 8)
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io.r_LoopBck := MODEROut.extract( 7)
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io.r_IFG := MODEROut.extract( 6)
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io.r_Pro := MODEROut.extract( 5)
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io.r_Iam := MODEROut.extract( 4)
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io.r_Bro := MODEROut.extract( 3)
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io.r_NoPre := MODEROut.extract( 2)
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io.r_TxEn := MODEROut.extract( 1) & (TX_BD_NUMOut > 0.U) // Transmission is enabled when there is at least one TxBD.
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io.r_RxEn := MODEROut.extract( 0) & (TX_BD_NUMOut < "h80".U) // Reception is enabled when there is at least one RxBD.
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io.r_IPGT := IPGTOut
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io.r_IPGR1 := IPGR1Out
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io.r_IPGR2 := IPGR2Out
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io.r_MinFL := PACKETLENOut(31,16)
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io.r_MaxFL := PACKETLENOut(15, 0)
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io.r_MaxRet := COLLCONFOut(19,16)
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io.r_CollValid := COLLCONFOut( 5, 0)
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io.r_TxFlow := CTRLMODEROut.extract(2)
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io.r_RxFlow := CTRLMODEROut.extract(1)
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io.r_PassAll := CTRLMODEROut.extract(0)
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io.r_MiiNoPre := MIIMODEROut.extract(8)
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io.r_ClkDiv := MIIMODEROut(7,0)
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io.r_WCtrlData := MIICOMMANDOut.extract(2)
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io.r_RStat := MIICOMMANDOut.extract(1)
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io.r_ScanStat := MIICOMMANDOut.extract(0)
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io.r_RGAD := MIIADDRESSOut(12,8)
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io.r_FIAD := MIIADDRESSOut( 4,0)
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io.r_CtrlData := MIITX_DATAOut(15,0)
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io.r_MAC := Cat( MAC_ADDR1Out(15,0), MAC_ADDR0Out(31,0) )
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io.r_HASH1 := HASH1Out
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io.r_HASH0 := HASH0Out
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io.r_TxBDNum := TX_BD_NUMOut
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io.r_TxPauseTV := TXCTRLOut(15,0)
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io.r_TxPauseRq := TXCTRLOut.extract(16)
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val SetTxCIrq_txclk_wire = Wire(Bool())
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val SetTxCIrq_sync1 = RegNext(SetTxCIrq_txclk_wire, false.B)
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val SetTxCIrq_sync2 = RegNext(SetTxCIrq_sync1, false.B)
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val SetTxCIrq_sync3 = RegNext(SetTxCIrq_sync2, false.B)
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val SetTxCIrq = RegNext(SetTxCIrq_sync2 & ~SetTxCIrq_sync3, false.B)
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val SetRxCIrq_rxclk_wire = Wire(Bool())
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val SetRxCIrq_sync1 = RegNext(SetRxCIrq_rxclk_wire, false.B)
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val SetRxCIrq_sync2 = RegNext(SetRxCIrq_sync1, false.B)
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val SetRxCIrq_sync3 = RegNext(SetRxCIrq_sync2, false.B)
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val SetRxCIrq = RegNext(SetRxCIrq_sync2 & ~SetRxCIrq_sync3, false.B)
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// Interrupt generation
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val irq_txb = RegInit(false.B)
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val irq_txe = RegInit(false.B)
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val irq_rxb = RegInit(false.B)
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val irq_rxe = RegInit(false.B)
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val irq_busy = RegInit(false.B)
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val irq_txc = RegInit(false.B)
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val irq_rxc = RegInit(false.B)
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when(io.TxB_IRQ){
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irq_txb := true.B
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}.elsewhen(INT_SOURCE_Wr & io.DataIn.extract(0)){
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irq_txb := false.B
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}
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when(io.TxE_IRQ){
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irq_txe := true.B
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} .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(1)){
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irq_txe := false.B
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}
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when(io.RxB_IRQ){
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irq_rxb := true.B
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} .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(2)){
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irq_rxb := false.B
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}
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||||
|
||||
when(io.RxE_IRQ){
|
||||
irq_rxe := true.B
|
||||
} .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(3)){
|
||||
irq_rxe := false.B
|
||||
}
|
||||
|
||||
when(io.Busy_IRQ){
|
||||
irq_busy := true.B
|
||||
} .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(4)){
|
||||
irq_busy := false.B
|
||||
}
|
||||
|
||||
|
||||
when(SetTxCIrq){
|
||||
irq_txc := true.B
|
||||
} .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(5)){
|
||||
irq_txc := false.B
|
||||
}
|
||||
|
||||
when(SetRxCIrq){
|
||||
irq_rxc := true.B
|
||||
} .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(6)){
|
||||
irq_rxc := false.B
|
||||
}
|
||||
|
||||
|
||||
withClockAndReset( io.TxClk.asClock, reset ) {
|
||||
// val ResetTxCIrq_sync1 = Reg(Bool())
|
||||
val ResetTxCIrq_sync2 = RegNext(SetTxCIrq_sync1, false.B)
|
||||
val SetTxCIrq_txclk = RegInit(false.B); SetTxCIrq_txclk_wire := SetTxCIrq_txclk
|
||||
|
||||
// Synchronizing TxC Interrupt
|
||||
when(io.TxCtrlEndFrm & io.StartTxDone & io.r_TxFlow){
|
||||
SetTxCIrq_txclk := true.B
|
||||
} .elsewhen(ResetTxCIrq_sync2){
|
||||
SetTxCIrq_txclk := false.B
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
withClockAndReset( io.RxClk.asClock, reset ) {
|
||||
val ResetRxCIrq_sync1 = RegNext(SetRxCIrq_sync2, false.B)
|
||||
val ResetRxCIrq_sync2 = RegNext(ResetRxCIrq_sync1, false.B)
|
||||
val ResetRxCIrq_sync3 = RegNext(ResetRxCIrq_sync2, false.B)
|
||||
val SetRxCIrq_rxclk = RegInit(false.B); SetRxCIrq_rxclk_wire := SetRxCIrq_rxclk
|
||||
|
||||
// Synchronizing RxC Interrupt
|
||||
when(io.SetPauseTimer & io.r_RxFlow){
|
||||
SetRxCIrq_rxclk := true.B
|
||||
} .elsewhen(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3)){
|
||||
SetRxCIrq_rxclk := false.B
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
// Generating interrupt signal
|
||||
io.int_o :=
|
||||
(irq_txb & INT_MASKOut.extract(0) ) |
|
||||
(irq_txe & INT_MASKOut.extract(1) ) |
|
||||
(irq_rxb & INT_MASKOut.extract(2) ) |
|
||||
(irq_rxe & INT_MASKOut.extract(3) ) |
|
||||
(irq_busy & INT_MASKOut.extract(4) ) |
|
||||
(irq_txc & INT_MASKOut.extract(5) ) |
|
||||
(irq_rxc & INT_MASKOut.extract(6) )
|
||||
|
||||
// For reading interrupt status
|
||||
INT_SOURCEOut := Cat( irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb )
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user