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同步测试完成

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This commit is contained in:
Ruige Lee
2025-04-30 17:09:30 +08:00
parent 031cffab24
commit 9d53e4ea82
3 changed files with 84 additions and 63 deletions
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9
src/main/scala/backBoard/shin/MasterParser.scala
View File

@@ -152,5 +152,14 @@ abstract class MasterParserBase extends Module{
class MasterParser extends MasterParserBase{
val deltaTimeStamp = Reg(UInt(32.W))
dontTouch(deltaTimeStamp)
val txStamps = Reg(UInt(32.W))
when( io.downOut.fire & io.downOut.bits.tlast ){
txStamps := io.timeStamp(31,0)
} .elsewhen( io.upIn.fire & io.upIn.bits.tlast & ~io.upIn.bits.tuser ){
deltaTimeStamp := io.timeStamp(31,0) - txStamps
}
}

43
src/main/scala/backBoard/shin/SlaveParser.scala
View File

@@ -546,6 +546,9 @@ trait SlaveParserSync{ this: SlaveParserBase =>
val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器
dontTouch(deltaFinal)
dontTouch(recoTimeStamp)
// recoTimeStamp = io.timeStamp + deltaFinal
// recoTimeStamp = io.timeStamp + mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
// recoTimeStamp = io.timeStamp + mstTimeStamp - downTimeStamp + (mstDeltaTimeStamp - slvDeltaTimeStamp ) >> 1
@@ -579,30 +582,30 @@ trait SlaveParserSync{ this: SlaveParserBase =>
when( isSync ){
when( syncCnt === 0.U ){
mstTimeStamp := Cat( downRecParser.io.data.bits, mstTimeStamp(55,0) )
} .elsewhen( syncCnt === 1.U ){
mstTimeStamp := Cat( mstTimeStamp(63,56), downRecParser.io.data.bits, mstTimeStamp(47,0) )
} .elsewhen( syncCnt === 2.U ){
mstTimeStamp := Cat( mstTimeStamp(63,48), downRecParser.io.data.bits, mstTimeStamp(39,0) )
} .elsewhen( syncCnt === 3.U ){
mstTimeStamp := Cat( mstTimeStamp(63,40), downRecParser.io.data.bits, mstTimeStamp(31,0) )
} .elsewhen( syncCnt === 4.U ){
mstTimeStamp := Cat( mstTimeStamp(63,32), downRecParser.io.data.bits, mstTimeStamp(23,0) )
} .elsewhen( syncCnt === 5.U ){
mstTimeStamp := Cat( mstTimeStamp(63,24), downRecParser.io.data.bits, mstTimeStamp(15,0) )
} .elsewhen( syncCnt === 6.U ){
mstTimeStamp := Cat( mstTimeStamp(63,16), downRecParser.io.data.bits, mstTimeStamp(7,0) )
} .elsewhen( syncCnt === 7.U ){
mstTimeStamp := Cat( mstTimeStamp(63, 8), downRecParser.io.data.bits )
} .elsewhen( syncCnt === 1.U ){
mstTimeStamp := Cat( mstTimeStamp(63,16), downRecParser.io.data.bits, mstTimeStamp(7,0) )
} .elsewhen( syncCnt === 2.U ){
mstTimeStamp := Cat( mstTimeStamp(63,24), downRecParser.io.data.bits, mstTimeStamp(15,0) )
} .elsewhen( syncCnt === 3.U ){
mstTimeStamp := Cat( mstTimeStamp(63,32), downRecParser.io.data.bits, mstTimeStamp(23,0) )
} .elsewhen( syncCnt === 4.U ){
mstTimeStamp := Cat( mstTimeStamp(63,40), downRecParser.io.data.bits, mstTimeStamp(31,0) )
} .elsewhen( syncCnt === 5.U ){
mstTimeStamp := Cat( mstTimeStamp(63,48), downRecParser.io.data.bits, mstTimeStamp(39,0) )
} .elsewhen( syncCnt === 6.U ){
mstTimeStamp := Cat( mstTimeStamp(63,56), downRecParser.io.data.bits, mstTimeStamp(47,0) )
} .elsewhen( syncCnt === 7.U ){
mstTimeStamp := Cat( downRecParser.io.data.bits, mstTimeStamp(55,0) )
} .elsewhen( syncCnt === 8.U ){
mstSlvDeltaTimeStamp := mstTimeStamp - downTimeStamp
mstDeltaTimeStamp := Cat( downRecParser.io.data.bits, mstDeltaTimeStamp(23, 0) )
} .elsewhen( syncCnt === 9.U ){
mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31,24), downRecParser.io.data.bits, mstDeltaTimeStamp(15,0) )
} .elsewhen( syncCnt === 10.U ){
mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31,16), downRecParser.io.data.bits, mstDeltaTimeStamp(7,0) )
} .elsewhen( syncCnt === 11.U ){
mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31, 8), downRecParser.io.data.bits )
} .elsewhen( syncCnt === 9.U ){
mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31,16), downRecParser.io.data.bits, mstDeltaTimeStamp(7,0) )
} .elsewhen( syncCnt === 10.U ){
mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31,24), downRecParser.io.data.bits, mstDeltaTimeStamp(15,0) )
} .elsewhen( syncCnt === 11.U ){
mstDeltaTimeStamp := Cat( downRecParser.io.data.bits, mstDeltaTimeStamp(23, 0) )
} .otherwise{
assert(false.B, "Wrong Sync SubMsg!\n")
}

95
tb/shinTest/ShinTopTb.v
View File

@@ -673,7 +673,7 @@ initial begin
end
end
for( integer i = 0; i < 512; i = i + 1 ) begin
for( integer i = 0; i < 516; i = i + 1 ) begin
@(posedge clock) #3
sram_w_0_enw = 1'b1;
sram_w_0_addrw = i;
@@ -694,7 +694,7 @@ initial begin
req_valid = 1'b1;
req_bits_txAddr = 0;
req_bits_rxAddr = 0;
req_bits_length = 512;
req_bits_length = 516;
@(posedge clock) #3
req_valid = 1'b0;
@@ -703,58 +703,67 @@ initial begin
// 同步
// #10000
#20000
// begin
begin
// dataBuf[0] = 8'h00;
// dataBuf[1] = 8'ha0;//heeader length 10
// dataBuf[2] = 8'h00;
// dataBuf[3] = 8'h00;
dataBuf[0] = 8'h01;
dataBuf[1] = 8'h40;//heeader length 20
dataBuf[2] = 8'h00;
dataBuf[3] = 8'h00;
// //子报文
// //设置顺序地址
// dataBuf[4] = 8'h0; //设备索引
// dataBuf[5] = 8'h0; //设备索引、类型
// dataBuf[6] = $random; //地址
// dataBuf[7] = $random; //地址
// dataBuf[8] = 8'hd0; //命令d 负载长度2
// dataBuf[9] = 8'd02; //负载长度2
// dataBuf[10] = 8'h0; //工作计数0
// dataBuf[11] = 8'h0; //工作计数0
//子报文
//设置同步
dataBuf[4] = 8'h0; //设备索引
dataBuf[5] = 8'h0; //设备索引、类型
dataBuf[6] = $random; //地址
dataBuf[7] = $random; //地址
dataBuf[8] = 8'he0; //命令d 负载长度2
dataBuf[9] = 8'h0c; //负载长度c
dataBuf[10] = 8'h0; //工作计数0
dataBuf[11] = 8'h0; //工作计数0
// dataBuf[12] = 8'h0; //负载
// dataBuf[13] = 8'h0; //负载
dataBuf[12] = timeStamp[7:0]; //负载
dataBuf[13] = timeStamp[15:8]; //负载
dataBuf[14] = timeStamp[23:16]; //负载
dataBuf[15] = timeStamp[31:24]; //负载
dataBuf[16] = timeStamp[39:32]; //负载
dataBuf[17] = timeStamp[47:40]; //负载
dataBuf[18] = timeStamp[55:48]; //负载
dataBuf[19] = timeStamp[63:56]; //负载
dataBuf[20] = s_ShinTop_Mst.masterParser.deltaTimeStamp[ 7: 0]; //负载
dataBuf[21] = s_ShinTop_Mst.masterParser.deltaTimeStamp[15: 8]; //负载
dataBuf[22] = s_ShinTop_Mst.masterParser.deltaTimeStamp[23:16]; //负载
dataBuf[23] = s_ShinTop_Mst.masterParser.deltaTimeStamp[31:24]; //负载
for( integer i = 0; i < 24; i = i + 1 ) begin
@(posedge clock) #3
sram_w_0_enw = 1'b1;
sram_w_0_addrw = i;
sram_w_0_dataw = dataBuf[i];
end
// for( integer i = 0; i < 14; i = i + 1 ) begin
// @(posedge clock) #3
// sram_w_0_enw = 1'b1;
// sram_w_0_addrw = i;
// sram_w_0_dataw = dataBuf[i];
// end
@(posedge clock) #3
sram_w_0_enw = 1'b0;
sram_w_0_addrw = 15'h0;
sram_w_0_dataw = 8'h0;
// @(posedge clock) #3
// sram_w_0_enw = 1'b0;
// sram_w_0_addrw = 15'h0;
// sram_w_0_dataw = 8'h0;
@(posedge clock) #3
txCmf = 1'b1;
@(posedge clock) #3
txCmf = 1'b0;
// @(posedge clock) #3
// txCmf = 1'b1;
// @(posedge clock) #3
// txCmf = 1'b0;
@(posedge clock) #3
req_valid = 1'b1;
req_bits_txAddr = 0;
req_bits_rxAddr = 0;
req_bits_length = 24;
// @(posedge clock) #3
// req_valid = 1'b1;
// req_bits_txAddr = 0;
// req_bits_rxAddr = 0;
// req_bits_length = 14;
@(posedge clock) #3
req_valid = 1'b0;
// @(posedge clock) #3
// req_valid = 1'b0;
// end
end
end