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增加测试代码，支持vqspi 4, bqspi 5

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This commit is contained in:
bacon
2026-02-07 10:45:58 +08:00
parent 41bb316926
commit 9d01b626d2
4 changed files with 91 additions and 27 deletions
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41
tb/shinTest/ShinTopSpiTb.v
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@@ -67,7 +67,7 @@ module ShinTopSpiTb(
wire qspi_sck; wire qspi_sck;
wire [3:0] qspi_mosi; wire [3:0] qspi_mosi;
//wire [40-1:0] qspi_miso; //wire [40-1:0] qspi_miso;
wire [(`ALL_DEV_NUM * 4 * 3 - 1):0] qspi_miso; wire [(`ALL_DEV_NUM * 4 * `QSPI_TYPE_NUM - 1):0] qspi_miso;
integer spidata_file; integer spidata_file;
integer c_line; integer c_line;
@@ -153,6 +153,18 @@ ShinTop s_ShinTop_Mst(
.io_aqspi_isDirIn(), .io_aqspi_isDirIn(),
.io_aqspi_csn(`AQSPI_CSN(0)), .io_aqspi_csn(`AQSPI_CSN(0)),
.io_vqspi_sck(qspi_sck),
.io_vqspi_mosi(qspi_mosi),
.io_vqspi_miso(`VQSPI_MISO(0)),
.io_vqspi_isDirIn(),
.io_vqspi_csn(`VQSPI_CSN(0)),
.io_bqspi_sck(qspi_sck),
.io_bqspi_mosi(qspi_mosi),
.io_bqspi_miso(`BQSPI_MISO(0)),
.io_bqspi_isDirIn(),
.io_bqspi_csn(`BQSPI_CSN(0)),
.io_isSoftReset(isSoftReset[0]), .io_isSoftReset(isSoftReset[0]),
.io_interrupt(io_int_sig[0]), .io_interrupt(io_int_sig[0]),
.io_latchPin_0(latch0), .io_latchPin_0(latch0),
@@ -478,8 +490,12 @@ end
reg [11:0] transCnt; reg [11:0] transCnt;
reg [11:0] byteCnt; reg [11:0] byteCnt;
reg [2:0] bitCnt; reg [2:0] bitCnt;
reg [11:0] length;
reg [16:0] idx;
`ifndef OLD_SPI_SUPPORT `ifndef OLD_SPI_SUPPORT
reg spi_1to4 = 1; reg spi_1to4 = 1;//(idx < (`ALL_DEV_NUM * 4));
`endif `endif
assign spi_mosi = exChangeRego[7]; assign spi_mosi = exChangeRego[7];
@@ -530,11 +546,6 @@ end
reg isReq = 0; reg isReq = 0;
reg isBusy = 0; reg isBusy = 0;
reg [11:0] length;
reg [16:0] idx;
always @(posedge clock) begin always @(posedge clock) begin
if( isReq & sck == 0 ) begin if( isReq & sck == 0 ) begin
isBusy <= #5 1'b1; isBusy <= #5 1'b1;
@@ -698,6 +709,7 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength, i
`endif `endif
idx <= sidx; idx <= sidx;
spi_1to4 = (idx < (`ALL_DEV_NUM * 4));
#5 #5
@(negedge sck) @(negedge sck)
@@ -946,11 +958,24 @@ end
`define ARRAY_IDX_OFF 4 `define ARRAY_IDX_OFF 4
`endif `endif
`ifdef USING_VQSPI
`define INTERFACE_IDX (`ALL_DEV_NUM * 4)//internal spi
`define ARRAY_IDX_OFF 4
`endif
`ifdef USING_BQSPI
`define INTERFACE_IDX (`ALL_DEV_NUM * 5)//internal spi
`define ARRAY_IDX_OFF 4
`endif
`define IF_IDX(idx) ((`INTERFACE_IDX)+(idx)) `define IF_IDX(idx) ((`INTERFACE_IDX)+(idx))
`define IF_IQSPI(idx) ((idx)) `define IF_IQSPI(idx) ((idx))
`define IF_OSPI(idx) ((`ALL_DEV_NUM) + (idx))
`define IF_OQSPI(idx) ((`ALL_DEV_NUM * 2) + (idx)) `define IF_OQSPI(idx) ((`ALL_DEV_NUM * 2) + (idx))
`define IF_AQSPI(idx) ((`ALL_DEV_NUM * 3) + (idx)) `define IF_AQSPI(idx) ((`ALL_DEV_NUM * 3) + (idx))
`define IF_OSPI(idx) ((`ALL_DEV_NUM) + (idx)) `define IF_VQSPI(idx) ((`ALL_DEV_NUM * 4) + (idx))
`define IF_BQSPI(idx) ((`ALL_DEV_NUM * 5) + (idx))
`define SPI_WRITE 8'h00 `define SPI_WRITE 8'h00
`define SPI_READ 8'h80 `define SPI_READ 8'h80

12
tb/shinTest/gen_pkt.py
View File

@@ -72,7 +72,7 @@ if __name__ == '__main__':
add_tc_2_runlist(rwregs.tc3()) add_tc_2_runlist(rwregs.tc3())
#''' #'''
''' #'''
add_tc_2_runlist(base.tc1()) add_tc_2_runlist(base.tc1())
add_tc_2_runlist(base.tc2()) add_tc_2_runlist(base.tc2())
add_tc_2_runlist(base.tc3()) add_tc_2_runlist(base.tc3())
@@ -80,6 +80,7 @@ if __name__ == '__main__':
add_tc_2_runlist(base.tc5()) add_tc_2_runlist(base.tc5())
add_tc_2_runlist(base.tc6()) add_tc_2_runlist(base.tc6())
add_tc_2_runlist(base.tc7()) add_tc_2_runlist(base.tc7())
'''
add_tc_2_runlist(base.tc8()) add_tc_2_runlist(base.tc8())
add_tc_2_runlist(base.tc9()) add_tc_2_runlist(base.tc9())
add_tc_2_runlist(base.tc10()) add_tc_2_runlist(base.tc10())
@@ -112,13 +113,12 @@ if __name__ == '__main__':
add_tc_2_runlist(broadcast.tc3()) add_tc_2_runlist(broadcast.tc3())
#''' #'''
#''' '''
#add_tc_2_runlist(sync.tc1()) add_tc_2_runlist(sync.tc1())
#add_tc_2_runlist(sync.tc2()) add_tc_2_runlist(sync.tc2())
#add_tc_2_runlist(sync.tc3()) add_tc_2_runlist(sync.tc3())
add_tc_2_runlist(sync.tc4()) add_tc_2_runlist(sync.tc4())
add_tc_2_runlist(sync.tc5()) add_tc_2_runlist(sync.tc5())
'''
add_tc_2_runlist(sync.tc6()) add_tc_2_runlist(sync.tc6())
add_tc_2_runlist(sync.tc7()) add_tc_2_runlist(sync.tc7())
add_tc_2_runlist(sync.tc8()) add_tc_2_runlist(sync.tc8())

8
tb/shinTest/pyutils/GenPkt.py
View File

@@ -271,7 +271,7 @@ def genCheckInsertTimeCode(wlog=True, dev_idx=0):
+ '''%s( (16'h24), (`SPI_READ), (2), (`IF_IDX(%d)) ); //检查替换时间戳替换地址寄存器\n'''%("`SPI_TRANS" if wlog else "spi_trans", dev_idx) + '''%s( (16'h24), (`SPI_READ), (2), (`IF_IDX(%d)) ); //检查替换时间戳替换地址寄存器\n'''%("`SPI_TRANS" if wlog else "spi_trans", dev_idx)
def genIFRwDataCode(dev, addr, isWrite = False, data_len=0, data = None, wlog=True, iface=4): def genIFRwDataCode(dev, addr, isWrite = False, data_len=0, data = None, wlog=True, iface=6):
spi_api="IF_IDX" spi_api="IF_IDX"
spi_offset = "`ARRAY_IDX_OFF" spi_offset = "`ARRAY_IDX_OFF"
if iface == 0: if iface == 0:
@@ -286,6 +286,12 @@ def genIFRwDataCode(dev, addr, isWrite = False, data_len=0, data = None, wlog=Tr
elif iface == 3: elif iface == 3:
spi_api = "IF_AQSPI" spi_api = "IF_AQSPI"
spi_offset = "4" spi_offset = "4"
elif iface == 4:
spi_api = "IF_VQSPI"
spi_offset = "4"
elif iface == 5:
spi_api = "IF_BQSPI"
spi_offset = "4"
else: else:
spi_api = "IF_IDX" spi_api = "IF_IDX"
spi_offset = "`ARRAY_IDX_OFF" spi_offset = "`ARRAY_IDX_OFF"

53
tb/shinTest/testcase/environment.py
View File

@@ -258,7 +258,19 @@ def __GenDevice(id, TerminateNode = False):
+"\t.io_aqspi_mosi(qspi_mosi),\n" +"\t.io_aqspi_mosi(qspi_mosi),\n"
+"\t.io_aqspi_miso(`AQSPI_MISO(%d)),\n"%(id + 1, ) +"\t.io_aqspi_miso(`AQSPI_MISO(%d)),\n"%(id + 1, )
+"\t.io_aqspi_isDirIn(),\n" +"\t.io_aqspi_isDirIn(),\n"
+"\t.io_aqspi_csn(`AQSPI_CSN(%d)),\n"%(id + 1, ) +"\t.io_aqspi_csn(`AQSPI_CSN(%d)),\n\n"%(id + 1, )
+"\t.io_vqspi_sck(qspi_sck),\n"
+"\t.io_vqspi_mosi(qspi_mosi),\n"
+"\t.io_vqspi_miso(`VQSPI_MISO(%d)),\n"%(id + 1, )
+"\t.io_vqspi_isDirIn(),\n"
+"\t.io_vqspi_csn(`VQSPI_CSN(%d)),\n\n"%(id + 1, )
+"\t.io_bqspi_sck(qspi_sck),\n"
+"\t.io_bqspi_mosi(qspi_mosi),\n"
+"\t.io_bqspi_miso(`BQSPI_MISO(%d)),\n"%(id + 1, )
+"\t.io_bqspi_isDirIn(),\n"
+"\t.io_bqspi_csn(`BQSPI_CSN(%d)),\n\n"%(id + 1, )
+"\t.io_isSoftReset(isSoftReset[%d]),\n"%(id + 1, ) +"\t.io_isSoftReset(isSoftReset[%d]),\n"%(id + 1, )
+"\t.io_interrupt(io_int_sig[%d]),\n"%(id + 1, ) +"\t.io_interrupt(io_int_sig[%d]),\n"%(id + 1, )
@@ -286,33 +298,46 @@ def __gen_slv_dev_predef(num):
spi_type_str = "USING_OQSPI" spi_type_str = "USING_OQSPI"
elif global_spi_type == 3: elif global_spi_type == 3:
spi_type_str = "USING_AQSPI" spi_type_str = "USING_AQSPI"
elif global_spi_type == 4:
spi_type_str = "USING_VQSPI"
elif global_spi_type == 5:
spi_type_str = "USING_BQSPI"
else: else:
spi_type_str = "USING_IQSPI" spi_type_str = "USING_IQSPI"
code_predef =("`define %s \n"%(spi_type_str, ) code_predef =("`define %s \n"%(spi_type_str, )
+"`define QSPI_TYPE_NUM 5 \n"
+"`define DEV_NUM %d //slave num\n"%(num, ) +"`define DEV_NUM %d //slave num\n"%(num, )
+"`define ALL_DEV_NUM (`DEV_NUM + 1) // slave + master\n" +"`define ALL_DEV_NUM (`DEV_NUM + 1) // slave + master\n"
+"`define SPI_CSN_NUM (`ALL_DEV_NUM * 4)\n\n" +"`define SPI_CSN_NUM (`ALL_DEV_NUM * 6)\n\n"
+"`define HW_SERIAL 48'h31303050584c //(48'h4c5850303031)\n\n" +"`define HW_SERIAL 48'h31303050584c //(48'h4c5850303031)\n\n"
+"`define IQSPI_PINS(N) (N*4+3):(N*4)\n" +"`define IQSPI_PINS(N) ((N ) * 4 + 3):((N ) * 4)\n"
+"`define EQSPI_PINS(N) ((N + `ALL_DEV_NUM)*4+3):((N + `ALL_DEV_NUM)*4)\n" +"`define EQSPI_PINS(N) ((N + `ALL_DEV_NUM ) * 4 + 3):((N + `ALL_DEV_NUM ) * 4)\n"
+"`define AQSPI_PINS(N) ((N + `ALL_DEV_NUM * 2)*4+3):((N + `ALL_DEV_NUM * 2)*4)\n\n" +"`define AQSPI_PINS(N) ((N + `ALL_DEV_NUM * 2) * 4 + 3):((N + `ALL_DEV_NUM * 2) * 4)\n"
+"`define VQSPI_PINS(N) ((N + `ALL_DEV_NUM * 3) * 4 + 3):((N + `ALL_DEV_NUM * 3) * 4)\n"
+"`define BQSPI_PINS(N) ((N + `ALL_DEV_NUM * 4) * 4 + 3):((N + `ALL_DEV_NUM * 4) * 4)\n\n"
+"`define IQSPI_MISO(N) qspi_miso[`IQSPI_PINS(N)]\n" +"`define IQSPI_MISO(N) qspi_miso[`IQSPI_PINS(N)]\n"
+"`define EQSPI_MISO(N) qspi_miso[`EQSPI_PINS(N)]\n" +"`define EQSPI_MISO(N) qspi_miso[`EQSPI_PINS(N)]\n"
+"`define AQSPI_MISO(N) qspi_miso[`AQSPI_PINS(N)]\n\n" +"`define AQSPI_MISO(N) qspi_miso[`AQSPI_PINS(N)]\n"
+"`define VQSPI_MISO(N) qspi_miso[`VQSPI_PINS(N)]\n"
+"`define BQSPI_MISO(N) qspi_miso[`BQSPI_PINS(N)]\n\n"
+"`define IQSPI_CSN_NUM(id) (id)\n" +"`define IQSPI_CSN_NUM(id) ((id))\n"
+"`define ESPI_CSN_NUM(id) ((id)+(`ALL_DEV_NUM))\n" +"`define ESPI_CSN_NUM(id) ((id)+(`ALL_DEV_NUM))\n"
+"`define EQSPI_CSN_NUM(id) ((id)+(`ALL_DEV_NUM)*2)\n" +"`define EQSPI_CSN_NUM(id) ((id)+(`ALL_DEV_NUM)*2)\n"
+"`define AQSPI_CSN_NUM(id) ((id)+(`ALL_DEV_NUM)*3)\n\n" +"`define AQSPI_CSN_NUM(id) ((id)+(`ALL_DEV_NUM)*3)\n"
+"`define VQSPI_CSN_NUM(id) ((id)+(`ALL_DEV_NUM)*4)\n"
+"`define BQSPI_CSN_NUM(id) ((id)+(`ALL_DEV_NUM)*5)\n\n"
+"`define IQSPI_CSN(id) spi_csn[`IQSPI_CSN_NUM(id)]\n" +"`define IQSPI_CSN(id) spi_csn[`IQSPI_CSN_NUM(id)]\n"
+"`define ESPI_CSN(id) spi_csn[`ESPI_CSN_NUM(id)]\n" +"`define ESPI_CSN(id) spi_csn[`ESPI_CSN_NUM(id)]\n"
+"`define EQSPI_CSN(id) spi_csn[`EQSPI_CSN_NUM(id)]\n" +"`define EQSPI_CSN(id) spi_csn[`EQSPI_CSN_NUM(id)]\n"
+"`define AQSPI_CSN(id) spi_csn[`AQSPI_CSN_NUM(id)]\n\n" +"`define AQSPI_CSN(id) spi_csn[`AQSPI_CSN_NUM(id)]\n"
+"`define VQSPI_CSN(id) spi_csn[`VQSPI_CSN_NUM(id)]\n"
+"`define BQSPI_CSN(id) spi_csn[`BQSPI_CSN_NUM(id)]\n\n"
) )
code_qspi_mux_init = "`define QSPI_MUX_MISO_INIT \\\n" code_qspi_mux_init = "`define QSPI_MUX_MISO_INIT \\\n"
@@ -327,7 +352,15 @@ def __gen_slv_dev_predef(num):
for i in range(num): for i in range(num):
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`AQSPI_MISO(%d) & ~{4{`AQSPI_CSN(%d)}}) |\\\n"%(i, i) code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`AQSPI_MISO(%d) & ~{4{`AQSPI_CSN(%d)}}) |\\\n"%(i, i)
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`AQSPI_MISO(%d) & ~{4{`AQSPI_CSN(%d)}})\n\n"%(num, num) code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`AQSPI_MISO(%d) & ~{4{`AQSPI_CSN(%d)}}) |\\\n"%(num, num)
for i in range(num):
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`VQSPI_MISO(%d) & ~{4{`VQSPI_CSN(%d)}}) |\\\n"%(i, i)
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`VQSPI_MISO(%d) & ~{4{`VQSPI_CSN(%d)}}) |\\\n"%(num, num)
for i in range(num):
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`BQSPI_MISO(%d) & ~{4{`BQSPI_CSN(%d)}}) |\\\n"%(i, i)
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`BQSPI_MISO(%d) & ~{4{`BQSPI_CSN(%d)}})\n\n"%(num, num)
code_qspi_mux_init = code_qspi_mux_init + code_qspi_mux_init_item code_qspi_mux_init = code_qspi_mux_init + code_qspi_mux_init_item