主站行为仅为axis到sram

src/main/scala/backBoard/shin/Interface.scala

@@ -1,19 +1,39 @@
-// package BACK
+package BACK
 
-// import chisel3._
+import chisel3._
-// import chisel3.util._
+import chisel3.util._
 
-// class InterfaceIO extends Module{
+class InterfaceIO extends Module{
 
-// }
+}
 
-// abstract class InterfaceBase extends Module{
+abstract class InterfaceBase extends Module{
-//   val io: InterfaceIO = IO(new InterfaceIO)
+  val io: InterfaceIO = IO(new InterfaceIO)
 
 
-// }
+
+  val isMstNSlv: Bool
+  val hwVersion: UInt
+  val hwSerial: UInt
+  val busRate: UInt
+  val RAMSize: UInt
+  val MMUNum: UInt
+
+  val nodeSeqAddr = Reg(UInt(16.W))
+  val nodeSetAddr = Reg(UInt(16.W))
+
+  val softReset = Reg(Bool())
+  val logicAddr = Reg(UInt(30.W))
+  val logicLength = Reg(UInt(16.W))
+  val phyAddr - Reg(UInt(16.W))
 
 
-// class Interface extends InterfaceBase{
+}
 
-// }
+
+
+
+
+class Interface extends InterfaceBase{
+
+}

src/main/scala/backBoard/shin/MasterParser.scala

@@ -1,19 +1,100 @@
-// package BACK
+package BACK
 
-// import chisel3._
+import chisel3._
-// import chisel3.util._
+import chisel3.util._
 
-// class MasterParserIO extends Module{
+class MasterParserIO extends Module{
+  val downOut = Decoupled(new AXIS_Bundle(8))
+  val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
 
-// }
+  val sram_r = Flipped(new ShareSRAMIO)
+  val sram_w = Flipped(new ShareSRAMIO)
 
-// abstract class MasterParserBase extends Module{
+  val req = Valid(new Bundle{
-//   val io: MasterParserIO = IO(new MasterParserIO)
+    val length  = UInt(12.W)
+  })
+  val rsp = Valid(new Bundle{
+    val isError = Bool()
+    val length  = UInt(12.W)
+  })
 
 
-// }
+
+}
+
+abstract class MasterParserBase extends Module{
+  val io: MasterParserIO = IO(new MasterParserIO)
+
+  val sendCnt = Reg(UInt(11.W))
+  val sendLen = Reg(UInt(11.W))
+
+  val reqReady = RegInit(true.B)
+  val sendAddr = Reg(UInt(12.W))
+
+  io.req.ready := reqReady
+
+  when( io.req.fire ){
+    reqReady := false.B
+  } .elsewhen( io.downOut.fire & sendCnt === sendLen ){
+    reqReady := true.B
+  }
+
+  when( io.req.fire ){
+    sendLen := io.req.bits.length
+    sendCnt := 0.U
+  } .elsewhen( io.downOut.fire ){
+    sendCnt := sendCnt + 1.U
+  }
+
+  when( reqReady ){
+    sendAddr := 0.U
+  } .elsewhen( io.downOut.fire ){
+    sendAddr := sendAddr + 1.U
+  }
+
+  io.sram_r.enr := 
+    io.req.fire | io.downOut.fire
+
+  io.sram_r.addr := Mux( io.req.fire, io.req.bits.addr, sendCnt )
+
+  io.downOut.valid := ~reqReady
+  io.downOut.bits.tdata := io.req.bits.datar
+  io.downOut.bits.tuser := false.B 
+  io.downOut.bits.tlast := sendCnt === sendLen
 
 
-// class MasterParser extends MasterParserBase{
 
-// }
+
+  val recAddr = Reg(UInt(12.W))
+
+  io.upIn.ready := true.B
+
+  io.sram_w.enw := io.upIn.fire
+  io.sram_w.addr := recAddr
+  io.sram_w.dataw := io.upIn.bits.tdata
+
+
+  when( io.upIn.fire ){
+    when( io.upIn.bits.tlast ){
+      recAddr := 0.U
+    } .otherwise{
+      recAddr := recAddr + 1.U
+    }
+  }
+
+  io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
+  io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tuser
+  io.rsp.bits.length  := recAddr
+
+
+
+
+
+
+
+}
+
+
+class MasterParser extends MasterParserBase{
+
+}