主站行为仅为axis到sram

src/main/scala/backBoard/shin/Interface.scala

@@ -1,19 +1,39 @@
-// package BACK
+package BACK
 
-// import chisel3._
-// import chisel3.util._
+import chisel3._
+import chisel3.util._
 
-// class InterfaceIO extends Module{
+class InterfaceIO extends Module{
 
-// }
+}
 
-// abstract class InterfaceBase extends Module{
-//   val io: InterfaceIO = IO(new InterfaceIO)
+abstract class InterfaceBase extends Module{
+  val io: InterfaceIO = IO(new InterfaceIO)
 
 
-// }
+
+  val isMstNSlv: Bool
+  val hwVersion: UInt
+  val hwSerial: UInt
+  val busRate: UInt
+  val RAMSize: UInt
+  val MMUNum: UInt
+
+  val nodeSeqAddr = Reg(UInt(16.W))
+  val nodeSetAddr = Reg(UInt(16.W))
+
+  val softReset = Reg(Bool())
+  val logicAddr = Reg(UInt(30.W))
+  val logicLength = Reg(UInt(16.W))
+  val phyAddr - Reg(UInt(16.W))
 
 
-// class Interface extends InterfaceBase{
+}
 
-// }
+
+
+
+
+class Interface extends InterfaceBase{
+
+}