From d5a52a651b0323bdaa260eeeae695461d5a0aabe Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Fri, 1 Aug 2025 11:15:24 +0800
Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E5=A4=8D=E4=BD=8Dcode?=
 =?UTF-8?q?=E7=89=B9=E6=80=A7?=
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---
 src/main/scala/backBoard/shin/Interface.scala | 27 ++++++++++++-------
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 7da6c2c..3a70354 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -42,21 +42,13 @@ class CommonRegisterBundle extends Bundle{
 
   val spiSel    = UInt(2.W)
 
+  val softResetCode = Vec(4, UInt(8.W))
 
   val intEnable = UInt(32.W)
   val intStatus = UInt(32.W)
   val intMode   = UInt(16.W)
 
 
-  // val upRecErrorCnt   = UInt(32.W)
-  // val downRecErrorCnt = UInt(32.W)
-  // val upForwardErrorCnt   = UInt(32.W)
-  // val downForwardErrorCnt = UInt(32.W)
-
-  // val qspiErrorCnt   = UInt(32.W)
-  // val forwardCnt     = UInt(32.W)
-  // val recByteCnt     = UInt(32.W)
-  // val forwardByteCnt = UInt(32.W)
 
   val statDownRecErrorCnt          = UInt(32.W)
   val statDownRecHeaderErrorCnt    = UInt(16.W)
@@ -271,6 +263,11 @@ abstract class InterfaceBase extends Module{
 
 
       Seq(
+        (addr === "h40".U ) -> cReg.softResetCode(1),
+        (addr === "h41".U ) -> cReg.softResetCode(1),
+        (addr === "h42".U ) -> cReg.softResetCode(2),
+        (addr === "h43".U ) -> cReg.softResetCode(3),
+
         (addr === "h70".U ) -> cReg.intEnable(7,0),
         (addr === "h71".U ) -> cReg.intEnable(15,8),
         (addr === "h72".U ) -> cReg.intEnable(23,16),
@@ -941,7 +938,17 @@ trait InterfaceSync{ this: InterfaceBase =>
 // }
 
 trait InterfaceSystem{ this: InterfaceBase =>
-  io.isSoftReset := ShiftRegister( isEnW & addrw === "h40".U, 16, false.B, true.B )
+  io.isSoftReset :=
+    cReg.softResetCode(0) === "h01".U &
+    cReg.softResetCode(1) === "h00".U &
+    cReg.softResetCode(2) === "h66".U &
+    cReg.softResetCode(3) === "h79".U
+
+  cReg.softResetCode(0) := RegEnable(dataw, 0.U, isEnW & addrw === "h40".U )
+  cReg.softResetCode(1) := RegEnable(dataw, 0.U, isEnW & addrw === "h41".U )
+  cReg.softResetCode(2) := RegEnable(dataw, 0.U, isEnW & addrw === "h42".U )
+  cReg.softResetCode(3) := RegEnable(dataw, 0.U, isEnW & addrw === "h43".U )
+
 
   cReg.intEnable :=
     Cat(