diff --git a/src/main/scala/backBoard/pico/BackSystem.scala b/src/main/scala/backBoard/pico/BackSystem.scala
index f7e2af0..6a3cea5 100644
--- a/src/main/scala/backBoard/pico/BackSystem.scala
+++ b/src/main/scala/backBoard/pico/BackSystem.scala
@@ -159,21 +159,21 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame
   gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr(13,12) === "b10".U & ~pico.io.mem.instr
 
   pico.io.mem.ready := 
-    Mux( pico.io.mem.instr, sram.io.mem.ready, 
+    // Mux( pico.io.mem.instr, sram.io.mem.ready, 
       Mux1H(Seq(
         (pico.io.mem.addr(13,12) === "b00".U ) -> sram.io.mem.ready,
         (pico.io.mem.addr(13,12) === "b01".U ) -> cdr.io.mem.ready,
         (pico.io.mem.addr(13,12) === "b10".U ) -> gpio.io.mem.ready,
       ))
-     )
+    //  )
   pico.io.mem.rdata := 
-    Mux( pico.io.mem.instr, sram.io.mem.rdata,
+    // Mux( pico.io.mem.instr, sram.io.mem.rdata,
       Mux1H(Seq(
         (pico.io.mem.addr(13,12) === "b00".U ) -> sram.io.mem.rdata,
         (pico.io.mem.addr(13,12) === "b01".U ) ->  cdr.io.mem.rdata,
         (pico.io.mem.addr(13,12) === "b10".U ) -> gpio.io.mem.rdata,
       )) 
-    )
+    // )
 
   sram.io.mem.wdata := pico.io.mem.wdata
    cdr.io.mem.wdata := pico.io.mem.wdata
diff --git a/src/main/scala/backBoard/pico/SimpleSRAM.scala b/src/main/scala/backBoard/pico/SimpleSRAM.scala
index 958d898..14081a8 100644
--- a/src/main/scala/backBoard/pico/SimpleSRAM.scala
+++ b/src/main/scala/backBoard/pico/SimpleSRAM.scala
@@ -41,16 +41,14 @@ class SimpleSRAM()(implicit p: Parameters) extends BackModule{
     // } .otherwise { io.mem.rdata := Cat( mem(io.mem.addr(11,2)).reverse ) }
   // }
 
-  val isReadAck = RegInit(false.B)
+  val isAck = RegInit(false.B)
   when( io.mem.fire ){
-    isReadAck := false.B
-  } .elsewhen( io.mem.valid & io.mem.wstrb === 0.U ){
-    isReadAck := true.B
+    isAck := false.B
+  } .elsewhen( io.mem.valid & ~isAck ){
+    isAck := true.B
   }
 
-  io.mem.ready := 
-    ( io.mem.wstrb =/= 0.U & true.B    ) |
-    ( io.mem.wstrb === 0.U & isReadAck )
+  io.mem.ready := isAck
 
 
 
diff --git a/src/main/scala/backBoard/pico/TLCDR.scala b/src/main/scala/backBoard/pico/TLCDR.scala
index bc69461..12605ed 100644
--- a/src/main/scala/backBoard/pico/TLCDR.scala
+++ b/src/main/scala/backBoard/pico/TLCDR.scala
@@ -191,7 +191,7 @@ trait TLCDRRx{ this: TLCDRBase =>
 
   rxFifo.reset := reset.asBool | isTLWriteSoftReset
 
-  rxFifo.io.deq.ready := isTLReadRxFifo
+  // rxFifo.io.deq.ready := isTLReadRxFifo
 
 
   when( isTLWriteSoftReset ){
@@ -217,9 +217,37 @@ class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCD
     dirSel := io.mem.wdata
   }
 
-  io.mem.ready := 
-    ( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) | 
-    ( io.mem.wstrb === 0.U & Mux( io.mem.addr(4,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) )
+  val isAck = RegInit(false.B)
+  val rdata = Reg(UInt(32.W))
+
+  when( io.mem.fire ){
+    isAck := false.B
+  } .elsewhen( io.mem.valid & ~isAck ){
+    when( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready ){
+      isAck := true.B
+    } .otherwise{
+      when( io.mem.addr(4,0) === "h1c".U & rxFifo.io.deq.valid ){
+        isAck := true.B
+        rdata := rxFifo.io.deq.bits
+        
+      } .elsewhen( io.mem.addr(4,0) === "h18".U ){
+        isAck := true.B
+        rdata := rxLen
+      } .elsewhen( io.mem.addr(4,0) === "h0".U ){
+        isAck := true.B
+        rdata := Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError)
+      }
+    }
+
+  }
+
+  rxFifo.io.deq.ready := io.mem.valid & ~isAck & io.mem.addr(4,0) === "h1c".U & rxFifo.io.deq.valid
+
+
+
+  io.mem.ready := isAck
+    // ( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) | 
+    // ( io.mem.wstrb === 0.U & Mux( io.mem.addr(4,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) )
 
 
 
@@ -229,12 +257,12 @@ class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCD
   io.interrupt(3) := intRxEnd
 
 
-  io.mem.rdata :=
-    Mux1H(Seq(
-      isTLReadStatus -> Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError),
-      isTLReadRxLen  -> rxLen,
-      isTLReadRxFifo -> rxFifo.io.deq.bits
-    ))
+  io.mem.rdata := rdata
+    // Mux1H(Seq(
+    //   isTLReadStatus -> ,
+    //   isTLReadRxLen  -> rxLen,
+    //   isTLReadRxFifo -> rxFifo.io.deq.bits
+    // ))