备份代码,尚未测试,实现全自动化生成verilog测试代码

This commit is contained in:
2025-08-02 15:59:42 +08:00
parent 3925cf3c0c
commit 9bfb5f919e
10 changed files with 249 additions and 86 deletions

View File

@@ -145,6 +145,12 @@ def tc2():
def tc3():
random.seed(int(time.time() * 1000))
gen_file_def = "error_pkt_tc03"
sm_idx = 0
tc_des = "发送错误的数据包,导致设备出问题,出问题的设备在没有恢复的情况下,采取直通状态。\\n" \
+ "清除中断后,错误消失,出问题的设备恢复正常。"
genPkt = GenPkt()
#-------------------------------------------------------------------------
#>>>>>>错误的数据包3
@@ -155,13 +161,15 @@ def tc3():
data.append(random.randint(0, 255))
genPkt.setPkt(2, data)
gen_file_def = "err_pkt3"
sm_idx = 0
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des))
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
+genWriteTransPktCode(gen_file_def, sm_idx)
+genTrgTransPktCode(gen_file_def, sm_idx)
+genReadAckPktCode(gen_file_def, sm_idx))
+genReadAckPktCode(gen_file_def, sm_idx)
+genTcEndFrameCode(gen_file_def))
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
return gen_file_def