备份代码,尚未测试,实现全自动化生成verilog测试代码

2025-08-02 15:59:42 +08:00
parent 3925cf3c0c
commit 9bfb5f919e
10 changed files with 249 additions and 86 deletions
--- a/tb/shinTest/testcase/environment.py
+++ b/tb/shinTest/testcase/environment.py
@@ -0,0 +1,41 @@
+from pyutils import *
+
+
+
+
+def bringup():
+    gen_file_def = "sys_bringup"
+    sm_idx = 0
+    tc_des = "发送错误的数据包，导致设备出问题，出问题的设备在没有恢复的情况下，采取直通状态。\\n" \
+           + "清除中断后，错误消失，出问题的设备恢复正常。"
+    
+    genPkt = GenPkt()
+
+    genPkt.clean()
+
+    genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des))
+
+    main_dev = [0x01, ]
+    slave_dev =[0x02, ]
+    genPkt.addAfterExc(genIFRwDataCode(0, 0x0, True, 1, main_dev)
+                       +"#5000\n"
+                       +genIFRwDataCode(1, 0x0, True, 1, slave_dev)
+                       +genIFRwDataCode(2, 0x0, True, 1, slave_dev)
+                       +genIFRwDataCode(3, 0x0, True, 1, slave_dev)
+                       +genIFRwDataCode(4, 0x0, True, 1, slave_dev)
+                       +genMessage("--读取寄存器，检查相关的配置")
+                       +genIFRwDataCode(1, 0x0, False, 1)
+                       +genIFRwDataCode(1, 0x0, False, 1)
+                       +genIFRwDataCode(2, 0x0, False, 1)
+                       +genIFRwDataCode(3, 0x0, False, 1)
+                       +genIFRwDataCode(4, 0x0, False, 1)
+                       )
+    
+    genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
+    add_tc_2_runlist(gen_file_def)
+
+
+
+def teardown():
+    #add_tc_2_runlist("")
+    pass