备份代码,尚未测试,实现全自动化生成verilog测试代码
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@@ -382,4 +382,6 @@ def genTcEndFrameCode(tcname):
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+'''\t\t$fdisplay(spidata_file, "该测试用例运行时间:%t\\n", _t_end - _t_start);\n'''\
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+f'''\t\t`END_TESTCASE("{__pre_gen_log_path}/{tcname}_result.log");\n'''\
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+'''\tend\n'''
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def genMessage(msg):
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return f'''\t\t$fdisplay(spidata_file, "{msg}");\n'''
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