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更新时序SPI

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This commit is contained in:
RuigeLee
2025-09-19 15:41:02 +08:00
parent 9fdd360854
commit 9b48306396
1 changed files with 34 additions and 34 deletions
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64
src/main/scala/backBoard/shin/NSpiInterface.scala
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@@ -20,6 +20,7 @@ abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{
val isEnW_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) } }
val spiLen = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) }
val spiLenTemp = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) }
val spiCnt = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(0.U(12.W)) }
val isSpiWrite = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) }
val isSpiRead = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) }
@@ -43,7 +44,7 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
qspi.miso := exRego(7, 4)
qspi.isDirIn := ~isSpiRead
qspi.isDirIn := isSpiWrite | (byteSel <= 3.U)
when( true.B ){
bitSel := ~bitSel
@@ -59,11 +60,11 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
exRegi := Cat( exRegi(3,0), qspi.mosi )
}
when( bitSel === 0.U ){
when((byteSel === 1.U || byteSel === 2.U || byteSel === 3.U ) ){
when( bitSel.andR ){
when((byteSel === 1.U || byteSel === 2.U ) ){
exRego := 0.U //地址1，cmd
} .elsewhen( isSpiRead ){
when( ~isPing_async ){ //取巧
when( isPing_async ){ //取巧
exRego := datar_sync(0)
} .otherwise{
exRego := datar_sync(1)
@@ -80,45 +81,42 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
spiCnt := spiCnt + 1.U
}
when( byteSel === 4.U & bitSel === 0.U ){
spiLen := Cat( exRegi, 0.U(8.W) )
} .elsewhen( byteSel === 4.U & bitSel.andR ){
spiLen := Cat( spiLen(11, 8), exRegi, 0.U(4.W) )
} .elsewhen( byteSel === 5.U & bitSel === 0.U ){
spiLen := Cat( spiLen(11, 4), exRegi )
when( byteSel === 2.U & bitSel.andR ){
spiLenTemp := Cat( qspi.mosi, 0.U(8.W) )
} .elsewhen( byteSel === 3.U & bitSel === 0.U ){
spiLenTemp := Cat( spiLenTemp(11, 8), qspi.mosi, 0.U(4.W) )
} .elsewhen( byteSel === 3.U & bitSel.andR ){
spiLen := Cat( spiLenTemp(11, 4), qspi.mosi )
}
when( bitSel === 0.U ){
when( isEnW_async(0) ){
addrw_async(0) := addrw_async(0) + 2.U
} .elsewhen( isEnW_async(1) ){
addrw_async(1) := addrw_async(1) + 2.U
} .elsewhen( bitSel === 0.U ){
when( byteSel === 1.U ){
addrw_async(0) := exRegi
addrw_async(1) := exRegi
} .elsewhen( byteSel === 2.U ) {
addrw_async(0) := Cat(addrw_async(0)(7,0), exRegi)
addrw_async(1) := Cat(addrw_async(1)(7,0), exRegi)
} .elsewhen( byteSel >= 5.U ){
when( ~isPing_async ){
addrw_async(0) := addrw_async(0) + 2.U
} .otherwise{
addrw_async(1) := addrw_async(1) + 2.U
}
addrw_async(1) := Cat(addrw_async(1)(7,0), exRegi) + 1.U
}
}
when( bitSel === 0.U ){
when( isEnR_async(0) ){
addrr_async(0) := addrr_async(0) + 2.U
} .elsewhen( isEnR_async(1) ){
addrr_async(1) := addrr_async(1) + 2.U
} .elsewhen( bitSel === 0.U ){
when( byteSel === 1.U ){
addrr_async(0) := exRegi
addrr_async(1) := exRegi
} .elsewhen( byteSel === 2.U ) {
addrr_async(0) := Cat(addrr_async(0)(7,0), exRegi)
addrr_async(1) := Cat(addrr_async(1)(7,0), exRegi)
}
} .otherwise{
when( byteSel >= 2.U ){
when( ~isPing_async ){
addrr_async(0) := addrr_async(0) + 2.U
} .otherwise{
addrr_async(1) := addrr_async(1) + 2.U
}
addrr_async(1) := Cat(addrr_async(1)(7,0), exRegi) + 1.U
}
}
@@ -151,13 +149,13 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
isEnR_async(1) := false.B
}
when( byteSel >= 5.U & bitSel === 0.U & (spiCnt < spiLen) & isSpiWrite ){
when( byteSel >= 4.U & bitSel.andR & (spiCnt < spiLen) & isSpiWrite ){
when( ~isPing_async ){
isEnW_async(0) := true.B
} .otherwise{
isEnW_async(1) := true.B
}
} .elsewhen( bitSel.andR ){
} .elsewhen( bitSel === 0.U ){
isEnW_async(0) := false.B
isEnW_async(1) := false.B
}
@@ -199,7 +197,7 @@ trait SyncSpiSync{ this: SyncSpiInterfaceBase =>
isPong_sync -> dataw_async(1),
))
when( io.isEnR ){
when( RegNext(io.isEnR, false.B) ){
when( RegNext(~isPong_sync, false.B) ){
datar_sync(0) := io.datar
} .otherwise{
@@ -207,7 +205,9 @@ trait SyncSpiSync{ this: SyncSpiInterfaceBase =>
}
}
when( io.isEnR | io.isEnW ){
when( ShiftRegister( qspi.csn, 2, false.B, true.B ) ){
isPong_sync := false.B
} .elsewhen( io.isEnR | io.isEnW ){
isPong_sync := ~isPong_sync
}