diff --git a/src/main/scala/backBoard/shin/NSpiInterface.scala b/src/main/scala/backBoard/shin/NSpiInterface.scala
index c2e38d6..08ebe9f 100644
--- a/src/main/scala/backBoard/shin/NSpiInterface.scala
+++ b/src/main/scala/backBoard/shin/NSpiInterface.scala
@@ -138,13 +138,16 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
     }    
   }
 
-  when( byteSel >= 2.U & bitSel.andR & (spiCnt < spiLen) & isSpiRead ){
+  when( 
+    (byteSel === 2.U & bitSel === 0.U & (spiCnt <= spiLen) & qspi.mosi === "h8".U) ||
+    (byteSel > 2.U   & bitSel === 0.U & (spiCnt <= spiLen) & isSpiRead)
+  ){
     when( ~isPing_async ){
       isEnR_async(0) := true.B
     } .otherwise{
       isEnR_async(1) := true.B
     }
-  } .elsewhen( bitSel === 0.U ){
+  } .elsewhen( bitSel.andR ){
     isEnR_async(0) := false.B
     isEnR_async(1) := false.B
   }