From 98b13e6b94302582f6e3785632fe75668a9a4f6d Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Wed, 27 Dec 2023 17:44:42 +0800
Subject: [PATCH] stage

---
 src/main/scala/backBoard/LocalRegisters.scala | 87 ++++++++++++++++---
 1 file changed, 77 insertions(+), 10 deletions(-)

diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala
index 36a24a5..1dc0952 100644
--- a/src/main/scala/backBoard/LocalRegisters.scala
+++ b/src/main/scala/backBoard/LocalRegisters.scala
@@ -3,27 +3,94 @@ package BACK
 import chisel3._
 import chisel3.util._
 
-
-class BackBoardSlvDigitalIO extends BackBoardSlvBase with BackBoardSlvDown with BackBoardSlvUp{
-  val in  = IO(Input(UInt(32.W)))
-  val out = IO(Output(UInt(32.W)))
-  val oe  = IO(Output(UInt(32.W)))
+/**
+  * 
+  * downReg(0) Status Setting
+  * upReg(0)   Status Feedback
+  * 
+  * downReg(1), downReg(2), leave blank
+  * upReg(1),   upReg(2),      leave blank
+  * 
+  * downReg(3) master ID
+  * upReg(3)   slvae ID
+  * 
+  * downReg(4), downReg(5), output Setting
+  * upReg(4),   upReg(5),   output Check
+  * 
+  * downReg(6), input Jitter
+  * downReg(7), leave blank
+  * upReg(6),   upReg(7)    input Feadback
+  */
+abstract class BackBoardSlvDigitalIOBase extends BackBoardSlvBase with BackBoardSlvDown with BackBoardSlvUp{
+  val in  = IO(Input(UInt(16.W)))
+  val out = IO(Output(UInt(16.W)))
 
 
+  out := Cat( downReg(5), downReg(4) )
 
-  out := Cat( (0 until 4).map{i => downReg(i)}.reverse )
-  oe  := Cat( (4 until 8).map{i => downReg(i)}.reverse )
-
+  upReg(4) := DontCare
+  upReg(5) := DontCare
 
   for( i <- 0 until 4 ) {
-    upReg(i) := in( i*8+7,8*i )
+    upReg(i) := 
   }
 
-
 }
 
+trait BackBoardSlvDigitalStatus{ this: BackBoardSlvDigitalIOBase =>
+  upReg(0) :=
+  upReg(3) := "ha5".U
+
+  := downReg(0)
+  := downReg(3)
+
+  // val globalTimer = RegInit(0.U())
+
+  // val watchDogCnt = RegInit(0.U(32.W))
+
+}
+
+trait BackBoardSlvDigitalInput{ this: BackBoardSlvDigitalIOBase =>
+  def smtBoederReg = 50.U -1.U
+  def inReg = VecInit(16, Bool())
 
 
+  val ( _, isInputCheck ) = Counter(Range( 0,1000), true.B, false.B) //100us in 100ns (10M)
+
+  val smtCnt    = for( i <- 0 until 16 ) yield RegInit(0.S(7.W))
+  val smtBoeder = for( i <- 0 until 16 ) yield WireDefault( smtBoederReg )
+
+
+  when( smtBoeder(i) === 0.U ){
+    inReg(i) := in(i)
+  } .elsewhen( isInputCheck ){
+    for( i <- 0 until 16 ){
+      when( in(i) === 1.U ){
+        when( smtCnt(i) < -smtBoeder(i) ){
+          smtCnt(i) := -smtBoeder(i) + 1.U
+        } .elsewhen( smtCnt(i) >= smtBoeder(i) ){
+          smtCnt(i) := smtBoeder(i)
+          inReg(i) := true.B
+        } .otherwise{
+          smtCnt(i) := smtCnt(i) + 1.U
+        }
+      } .otherwise{
+        when( smtCnt(i) <= -smtBoeder(i) ){
+          smtCnt(i) := -smtBoeder(i)
+          inReg(i) := false.B
+        } .elsewhen( smtCnt(i) >  smtBoeder(i) ){
+          smtCnt(i) := smtBoeder(i) - 1.U
+        } .otherwise{
+          smtCnt(i) := smtCnt(i) - 1.U
+        }
+      }
+    }
+  }
+}
+
+trait BackBoardSlvDigitalOutput{ this: BackBoardSlvDigitalIOBase =>
+  
+}
 
 
 // trait LocalRegisters { this: BackBoardSlvBase =>