接入TL2CDR

2025-01-10 15:25:10 +08:00
parent 134440812b
commit 981b492a8b
2 changed files with 4 additions and 4 deletions
--- a/src/main/scala/backBoard/ebus/CDROut.scala
+++ b/src/main/scala/backBoard/ebus/CDROut.scala
@@ -28,8 +28,8 @@ class CDROut extends Module{
  def STATE_FCS = 3.U


-  val ETH_PRE = "h55".U
-  val ETH_SFD = "hD5".U
+  val ETH_PRE = "h55".U(8.W)
+  val ETH_SFD = "hD5".U(8.W)

  val stateNext = Wire(UInt(2.W))
  val stateCurr = RegNext( stateNext, 0.U )