From 9773752cc86be3a40c39d69a641dd599d18370cf Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Wed, 27 Aug 2025 15:55:09 +0800
Subject: [PATCH] =?UTF-8?q?=E4=B8=8A=E4=B8=8B=E8=A1=8C=E4=BA=A4=E6=8D=A2?=
 =?UTF-8?q?=E7=89=B9=E6=80=A7?=
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---
 src/main/scala/backBoard/shin/Interface.scala | 35 +++++++++++++++++++
 .../scala/backBoard/shin/MstSlvSwitch.scala   |  2 +-
 2 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 0270c66..b4def35 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -52,6 +52,10 @@ class CommonRegisterBundle extends Bundle{
   val refTop = UInt(3.W)
   val bias   = UInt(2.W)
 
+  val dwupEx   = UInt(16.W)
+  val b8b4Sel  = UInt(16.W)
+  val cdrParam = UInt(16.W)
+
 
   val softResetCode = Vec(4, UInt(8.W))
 
@@ -295,7 +299,20 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
         (addr === ("h48".U(16.W) + i.U) ) -> cReg.xtal( 8*i+7,8*i+0 )
       }) ++
 
+
+      ((0 until 2).map{ i =>
+        (addr === ("h4c".U(16.W) + i.U) ) -> cReg.b8b4Sel( 8*i+7,8*i+0 )
+      }) ++
+
+      ((0 until 2).map{ i =>
+        (addr === ("h4e".U(16.W) + i.U) ) -> cReg.cdrParam( 8*i+7,8*i+0 )
+      }) ++
+
       Seq(
+        (addr === "h4a".U ) -> cReg.dwupEx.extrace(0),
+        (addr === "h4c".U ) -> cReg.b8b4Sel.extrace(0),
+        (addr === "h4e".U ) -> cReg.cdrParam(7,0),
+
         (addr === "h50".U ) -> cReg.anamuxSel,
         (addr === "h51".U ) -> cReg.ldo2p5,
         (addr === "h52".U ) -> cReg.ldo1p1,
@@ -1082,6 +1099,24 @@ trait InterfaceSystem{ this: InterfaceBase =>
   cReg.softResetCode(3) := RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h43".U )
 
 
+  cReg.dwupEx   := 
+    Cat(
+      RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4b".U ),
+      RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4a".U )
+    )
+
+  cReg.b8b4Sel  := 
+    Cat(
+      RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4d".U ),
+      RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4c".U )
+    )
+  cReg.cdrParam := 
+    Cat(
+      RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4f".U ),
+      RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4e".U )
+    )
+
+
   cReg.intEnable :=
     Cat(
       1.U(1.W), //复位中断，时钟为1 //31 上电复位
diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala
index 07eeda8..a3286b0 100644
--- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala
+++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala
@@ -472,7 +472,7 @@ class MstSlvSwitch extends MstSlvSwitchBase
 with MstSlvSwitchMaster
 with MstSlvSwitchSlave
 with MstSlvSwitchWatchDog{
-
+  val isDwUpEx = interface.cReg.dwupEx
 
 
   when( interface.io.cReg.modeSel === false.B ){ //slave