diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 0548824..630f6a7 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -95,10 +95,12 @@ trait CDRInAxis{ this: CDRInBase =>
   val operation  = header(15,8)
   val param      = header( 7,0)
 
-
+  val isArbLock: Bool
+  val isPrebleLock = RegInit(false.B)
+  
   stateNext := 
     Mux1H(Seq(
-      (stateCurr === STATE_IDLE)    -> ( Mux( isArbLock & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
+      (stateCurr === STATE_IDLE)    -> ( Mux( isPrebleLock & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
       (stateCurr === STATE_HEADER)  -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ),
       (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U)  ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD  )), // PAYLOAD
       (stateCurr === STATE_CRC)     -> ( Mux( (byteCnt === 3.U)            & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC
@@ -106,15 +108,21 @@ trait CDRInAxis{ this: CDRInBase =>
 
 
 
-  val isArbLock: Bool
 
-  when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isArbLock ){ //first align
+
+  when( shiftData === ETH_PRE & stateCurr === STATE_IDLE & isArbLock ){
+    isPrebleLock := true.B
+  } .elsewhen( (shiftData =/= "h55".U & shiftData =/= "haa".U) | ~isArbLock ){
+    isPrebleLock := false.B
+  }
+
+  when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isPrebleLock ){ //first align
     bitCnt := 0.U
   } .otherwise{ 
     bitCnt := bitCnt + 1.U
   }
 
-  when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isArbLock ){ //first align
+  when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isPrebleLock ){ //first align
     byteCnt := 0.U
   } .elsewhen( bitCnt === 7.U ){
     when( stateCurr === STATE_HEADER ){