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spi优化

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This commit is contained in:
Ruige Lee
2025-08-28 18:00:20 +08:00
parent 4b88e4937d
commit 955fda6d05
1 changed files with 28 additions and 19 deletions
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47
src/main/scala/backBoard/shin/SpiInterface.scala
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@@ -44,8 +44,6 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
val isSckPosedgeNext = ShiftRegisters(isSckPosedge, 2, false.B, true.B)
val isSckNegedge = ShiftRegister(isSckPosedge, 3, false.B, true.B) //shiftSCK(2) & ~shiftSCK(1) //确定下降沿放数据到数据线上
val exRego = Reg(UInt(8.W))
val exRegi = Reg(UInt(8.W))
@@ -64,15 +62,12 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val byteSelNext = RegNext(byteSel)
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext.andR & isSpiWrite & byteSelNext >= 3.U
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
io.dataw := exRegi
io.addrr := addrr
io.addrw := addrw
// io.addrSel :=
// Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
// val readData = RegEnable(io.datar, io.isEnR)
when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -85,17 +80,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrw := 0.U
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
addrw := exRegi
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
addrw := Cat(addrw(7,0), exRegi)
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){
addrw := addrw + 1.U
}
}
@@ -113,6 +98,7 @@ class SSpiInterface extends SpiInterfaceBase{
sck := spi.sck
csn := spi.csn
io.isEnR :=
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & shiftMOSI(1) === 1.U & byteSelNext === 2.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & isSpiRead & byteSelNext >= 3.U)
@@ -169,7 +155,19 @@ class SSpiInterface extends SpiInterfaceBase{
}
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrw := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrw := Cat( exRegi(6,0), shiftMOSI(1) )
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrw := Cat(addrw(7,0), exRegi(6,0), shiftMOSI(1) )
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(0) & byteSelNext >= 3.U & bitSelNext.andR ){
addrw := addrw + 1.U
}
}
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext.andR & isSpiWrite & byteSelNext >= 3.U
}
class QSpiInterface extends SpiInterfaceBase{
@@ -182,11 +180,11 @@ class QSpiInterface extends SpiInterfaceBase{
qspi.isDirIn := ~isSpiRead
io.isEnR :=
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & shiftMOSI(1) === "b1000".U & byteSelNext === 2.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & shiftMOSI(2) === "b1000".U & byteSelNext === 2.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & isSpiRead & byteSelNext >= 3.U)
when( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSelNext === 2.U & bitSelNext === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := shiftMOSI(1).extract(3)
spiCmd := shiftMOSI(2).extract(3)
}
when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -235,6 +233,17 @@ class QSpiInterface extends SpiInterfaceBase{
}
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrw := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrw := Cat( exRegi(3,0), shiftMOSI(1) )
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrw := Cat(addrw(7,0), exRegi(3,0), shiftMOSI(1) )
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(0) & byteSelNext >= 3.U & bitSelNext.andR ){
addrw := addrw + 1.U
}
}
}