新增16，17，18，19号中断

src/main/scala/backBoard/shin/Interface.scala

@@ -177,6 +177,7 @@ class InterfaceIO extends Bundle{
   val intHWTrig   = Input(Vec(2, Bool()))
   val intHWClr    = Output(Vec(2, Bool()))
   val intSlvTrig  = Input(Vec(8, Bool()))
+  val intTransEnd = Input(Vec(4,Bool()))
 
   val interrupt = Output(Bool())
 
@@ -1002,6 +1003,13 @@ trait InterfaceSystem{ this: InterfaceBase =>
     }
   }
 
+  //传输完成请求 16,17,18,19
+  for( i <- 0 until 4 ){
+    when( io.intTransEnd(i) ){
+      intStatus(16+i) := true.B
+    }
+  }
+
   //下行接收硬件错误
   when( io.intHWTrig(0) ){
     intStatus(29) := true.B
@@ -1040,6 +1048,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
     false.B | //主站发送周期到了
     (~RegNext(io.wdtTrigger.reduce(_|_), false.B) & io.wdtTrigger.reduce(_|_) & cReg.intEnable(4)) | //主站接收看门狗溢出
     (0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
+    (0 until 4).map{ i => io.intTransEnd(i) & cReg.intEnable(16+i)}.reduce(_|_) | //传输完成请求 16,17,18,19
     io.intHWTrig(0) | //下行接收硬件错误
     io.intHWTrig(1)   //上行接收硬件错误
 

src/main/scala/backBoard/shin/ShinTop.scala

@@ -51,6 +51,11 @@ abstract class ShinTopBase extends Module{
 
   interface.io.latchPin  := io.latchPin
 
+  interface.io.intTransEnd(0) := downCDRIn.io.axis.fire  & downCDRIn.io.axis.bits.tlast
+  interface.io.intTransEnd(1) := downCDROut.io.axis.fire & downCDROut.io.axis.bits.tlast
+  interface.io.intTransEnd(2) := upCDRIn.io.axis.fire    & upCDRIn.io.axis.bits.tlast
+  interface.io.intTransEnd(3) := upCDROut.io.axis.fire   & upCDROut.io.axis.bits.tlast
+
   io.ledTest := RegNext( Cat(slaveParser.io.intHWTrig(0), slaveParser.io.intHWTrig(1)) )
   
   io.isSoftReset := interface.io.isSoftReset