From 946bbd8c3522e71523702e3047b22c90aea2ef3e Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Tue, 19 Aug 2025 16:03:12 +0800
Subject: [PATCH] =?UTF-8?q?=E4=B8=BB=E7=AB=99=E5=A2=9E=E5=8A=A019=E5=8F=B7?=
 =?UTF-8?q?=E4=B8=AD=E6=96=AD=E7=94=A8=E4=BA=8E=E6=8F=90=E7=A4=BA=E4=B8=8A?=
 =?UTF-8?q?=E8=A1=8CCRC=E9=94=99=E8=AF=AF?=
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---
 src/main/scala/backBoard/shin/Interface.scala | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 54480c3..7ab88af 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -637,12 +637,12 @@ trait InterfaceMCUop{ this: InterfaceBase =>
   mReg.rxSM     := RegEnable( dataw(4,3), 0.U(2.W), isEnW & addrw === "h20".U )
   // mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrw === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrw === "h21".U ) )
 
-  val isMstRecCRCErr = RegInit(0.U(4.W))
-  mReg.isRecCRCErr := isMstRecCRCErr
+  val mReg_isRecCRCErr = RegInit(0.U(4.W))
+  mReg.isRecCRCErr := mReg_isRecCRCErr
   when( isEnW & addrw === "h22".U(16.W) ){
-    isMstRecCRCErr := 0.U
+    mReg_isRecCRCErr := 0.U
   } .elsewhen( io.upRecStat.isCRCError & isMstMode ){
-    isMstRecCRCErr := isMstRecCRCErr | (1.U << mReg.rxSM)
+    mReg_isRecCRCErr := mReg_isRecCRCErr | (1.U << mReg.rxSM)
   }
 
 
@@ -1149,12 +1149,20 @@ trait InterfaceSystem{ this: InterfaceBase =>
   }
 
   //传输完成请求 16,17,18,19
+  //主站状态下19为上行crc接收错误
   for( i <- 0 until 4 ){
     when( io.intTransEnd(i) ){
       intStatus(16+i) := true.B
     }
   }
 
+  //override
+  //主站状态下19为上行crc接收错误
+  val isMstRecCRCErr = io.upRecStat.isCRCError & isMstMode
+  when( isMstRecCRCErr ){
+    intStatus(19) := true.B
+  }
+
   //下行接收硬件错误
   when( io.intHWTrig(0) ){
     intStatus(29) := true.B
@@ -1195,6 +1203,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
     (~RegNext(isWdtTrigAndEnable, false.B) & isWdtTrigAndEnable & cReg.intEnable(4)) | //主站接收看门狗溢出
     (0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
     (0 until 4).map{ i => io.intTransEnd(i) & cReg.intEnable(16+i)}.reduce(_|_) | //传输完成请求 16,17,18,19
+    isMstRecCRCErr | //override //主站状态下19为上行crc接收错误 //不会同时发生
     io.intHWTrig(0) | //下行接收硬件错误
     io.intHWTrig(1)   //上行接收硬件错误